1©2016 Integrated Device Technology, Inc. Revision C September 28, 2016
General Description
The 83905I is a low skew, 1-to-6 LVCMOS / LVTTL Fanout Buffer.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50 series or parallel terminated transmission lines. The
effective fanout can be increased from 6 to 12 by utilizing the
ability of the outputs to drive two series terminated lines.
The 83905I is characterized at full 3.3V, 2.5V, and 1.8V, mixed
3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating supply
modes. Guaranteed output and part-to-part skew characteristics
along with the 1.8V output capabilities makes the 83905I ideal for
high performance, single ended applications that also require a
limited output voltage.
Pin Assignments
Features
Six LVCMOS / LVTTL outputs
Outputs able to drive 12 series terminated lines
Crystal Oscillator Interface
Crystal input frequency range: 10MHz to 40MHz
Output skew: 80ps (maximum)
RMS phase jitter @ 25MHz, (100Hz – 1MHz): 0.26ps (typical),
V
DD
= V
DDO
= 2.5V
Offset Noise Power
100Hz.................-129.7 dBc/Hz
1kHz...................-144.4 dBc/Hz
10kHz.................-147.3 dBc/Hz
100kHz...............-157.3 dBc/Hz
5V tolerant enable inputs
Synchronous output enables
Operating power supply modes:
Full 3.3V, 2.5V, 1.8V
Mixed 3.3V core/2.5V output operating supply
Mixed 3.3V core/1.8V output operating supply
Mixed 2.5V core/1.8V output operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Block Diagram
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XTAL_IN
ENABLE1
BCLK5
V
DDO
BCLK4
GND
BCLK3
V
DD
BCLK2
GND
BCLK1
V
DDO
BCLK0
GND
ENABLE2
XTAL_OUT
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
SYNCHRONIZE
SYNCHRONIZE
BCLK
0
BCLK
1
BCLK
2
BCLK
3
BCLK
4
BCLK
5
XTAL_IN
X
TAL_OUT
ENABLE 1
ENABLE 2
83905I
Datasheet
Low Skew, 1:6 Crystal Interface to
LVCMOS/ LVTTL Fanout Buffer
2©2016 Integrated Device Technology, Inc. Revision C September 28, 2016
83905I Datasheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Table 2. Pin Characteristics
Number Name Type Description
1 XTAL_OUT Output Crystal oscillator interface. XTAL_OUT is the output.
2 ENABLE2 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3.
3 GND Power Power supply ground.
4 BCLK0 Output Clock output. LVCMOS/LVTTL interface levels.
5V
DDO
Power Output supply pin.
6 BCLK1 Output Clock output. LVCMOS/LVTTL interface levels.
7 GND Power Power supply ground.
8 BCLK2 Output Clock output. LVCMOS/LVTTL interface levels.
9V
DD
Power Power supply pin.
10 BCLK3 Output Clock output. LVCMOS/LVTTL interface levels.
11 GND Power Power supply ground.
12 BCLK4 Output Clock output. LVCMOS/LVTTL interface levels.
13 V
DDO
Power Output supply pin.
14 BCLK5 Output Clock output. LVCMOS/LVTTL interface levels.
15 ENABLE1 Input Clock enable. LVCMOS/LVTTL interface levels. See Table 3.
16 XTAL_IN Input Crystal oscillator interface. XTAL_IN is the input.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation
Capacitance
(per output)
V
DDO
= 3.465V 19 pF
V
DDO
= 2.625V 18 pF
V
DDO
= 2.0V 16 pF
R
OUT
Output Impedance
V
DDO
= 3.3V ± 5% 7
V
DDO
= 2.5V ± 5% 7
V
DDO
= 1.8V ± 0.2V 10
3©2016 Integrated Device Technology, Inc. Revision C September 28, 2016
83905I Datasheet
Function Table
Table 3. Output Enable and Clock Enable Function Table
Figure 1. Enable Timing Diagram
Control Inputs Outputs
ENABLE 1 ENABLE2 BCLK[0:4] BCLK5
0 0 LOW LOW
0 1 LOW Toggling
1 0 Toggling LOW
1 1 Toggling Toggling
BCLK5
BCLK[0:4]
ENABLE2
ENABLE1

83905AGILFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer Low Skew 1:5 Fanout Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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