16©2016 Integrated Device Technology, Inc. Revision C September 28, 2016
83905I Datasheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 83905I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 83905I is the sum of the core power plus the analog power plus the power dissipated due to the load.
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
• Power (core)
MAX
= V
DD_MAX
* (I
DD
+ I
DDO
) = 3.465V *(10mA + 5mA) = 51.9mW
• Output Impedance R
OUT
Power Dissipation due to Loading 50 to V
DD
/2
Output Current I
OUT
= V
DD_MAX
/ [2 * (50 + R
OUT
)] = 3.465V / [2 * (50 + 7)] = 30.4mA
• Power Dissipation on the R
OUT
per LVCMOS output
Power (R
OUT
) = R
OUT
* (I
OUT
)
2
= 7 * (30.4mA)
2
= 6.5mW per output
• Total Power Dissipation on the R
OUT
Total Power (R
OUT
) = 6.5mW * 6 = 39mW
Dynamic Power Dissipation at 25MHz
Power (25MHz) = C
PD
* Frequency * (V
DD
)
2
= 19pF * 25MHz * (3.465V)
2
= 5.70mW per output
Total Power (25MHz) = 5.70mW * 6 = 34.2mW
Total Power Dissipation
• Total Power
= Power (core)
MAX
+ Total Power (R
OUT
) + Total Power (25MHz)
= 51.98mW + 39mW + 34.2mW
= 125.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 89°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.125W * 89°C/W = 96.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the
type of board (multi-layer).
Table 7. Thermal Resistance
JA
for 16-Lead TSSOP, Forced Convection
JA
by Velocity
Linear Feet per Minute 0 200 500
Single-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 118.2°C/W 106.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 89.0°C/W 81.8°C/W 78.1°C/W
NOTE: Most modern PCB designs use milti-layered boards. The data in the second row pertains to most designs.
