FAN5230
10 REV. 2.8.5 10/17/01
This mode of operation implies the use of a push button
switch between SDWN and Vin. Pushing the button allows
(for the duration of the contact) to power the 3.3V-ALWAYS
and 5V-ALWAYS long enough for the uC to power up and in
turn latch the SDWN pin high.
Once the SDWN is high then the ALWAYS voltages are en-
abled to go high if the respective SDN3.3 and SDN5 go high.
MAIN 3.3V and 5V Softstart, Sequencing and
Stand-by
Softstart of the 3.3V and 5V converters is accomplished by
means of an external capacitor between pins SDN3.3 (SDN5)
and ground.
The 3.3V (5V) main converter is turned ON if SDWN and
SDN3.3 (SDN5) are both high and is turned off if either SDWN
or SDN3.3 (SDN5) is low.
Stand-by mode is defined as the condition by which V-Mains
are OFF and V-ALWAYS are ON (SDWN=1 and
SDN3.3=SDN5=0).
ALWAYS mode of Operation
If it is desired that 5V-ALWAYS and 3.3V-ALWAYS are always
ON then the SDWN pin must be connected to Vin permanently.
This way the two ALWAYS regulators come up as soon as there
is power while the state of the Main regulators can be controlled
via the SDN5 and SDN3.3 pins.
Sequencing Table
3.3V and 5V Light Load Mode
The 3.3V and 5V converters are synchronous bucks, and can
operate in two quadrants, this means that the ripple current is
constant and independent of the load current. At light loads,
this ripple current translates into poor efficiency, since it
causes circulating current losses in the MOSFETs. To opti-
mize the efficiency at light loads, then, the FAN5230
switches from normal operation to a special light load mode
after an 8 clock pulse delay. This prevents false triggering
when the voltage across the on-state low-side MOSFET goes
positive. Vice-versa when this voltage becomes negative the
FAN5230 switches back to PWM operation. The current
threshold for switch to and from light load is therefore:
Ith = Iripplepeak
In light load mode, the FAN5230 switches from PWM (pulse
width modulation) to PFM (pulse frequency modulation),
which reduces the gate drive current.
As the load current becomes very light, the FAN5230 begins
pulse skipping, but remains synchronized with the clock. See
next section for low side drive management.
Low Side Driver Forcing in Light Load
During light load operation, the Low Side Driver (LSD) is
traditionally turned permanently OFF to avoid current inver-
sion in the inductor and associated efficiency losses. At the
same time the low side driver also needs to be turned ON in
order to a) measure current (current is sensed on the low side
driver) and b) assure proper operation of the charge pump,
especially under low current and low input voltage condi-
tions. In order to accomplish all the above, when the circuit
enters hysteretic operation the LSD is kept “ON” to re-circu-
late positive and decaying currents (corresponding to nega-
tive drops across low side driver Rdson) and turned off as
soon as current crosses zero (corresponding to drop across
Rdson becoming positive). This way the low side driver is
utilized in “partial duty” or as “active zero drop diode”
(compared to classic light load operation in which the LSD is
turned permanently OFF) allowing more functionality with-
out loss in efficiency.
3.3V Voltage Adjustment
The output voltage of the 3.3V converter can be increased by
as much as 10% by inserting a resistor divider in the feedback
line. The feedback pin impedance is about 66K. Thus, for
example, to increase the output of the 3.3V converter by 10%,
use a 2.21K/33.2K divider.
Note that the output of the 5V regulator cannot be adjusted.
The feedback line of the 5V regulator is used internally as a
5V supply and, therefore, cannot tolerate any impedance in
series with it.
3.3V and 5V Main Overvoltage Protection
(Soft Crowbar)
When the output voltage of the 3.3V (or the 5V) converter
exceeds approximately 115% of nominal, the converter enters
the over-voltage (OV) protection mode, with the goal of pro-
tecting the load from damage. During operation, severe load
dump or a short of an upper MOSFET could cause the output
voltage to increase significantly over normal operation range
without circuit protection. When the output exceeds the over-
voltage threshold, the over-voltage comparator forces the
lower gate driver high and turns the lower MOSFET on. This
will pull down the output voltage and eventually may blow the
battery fuse. As soon as output voltage drops below the
threshold, OVP comparator is disengaged.
The OVP scheme also provides a soft crowbar function
(bang-bang control followed by blow of the fuse) which
helps to tackle severe load transients but does not invert out-
put voltage when activated—a common problem for OVP
schemes with a latch. The prevention of output inversion
eliminates the need for a Schottky diode across the load.
SDN5 SDN3.3 SDWN
3V&5V
ALWAYS
5V
MAIN
3.3V
MAIN
X X 0 0 0 0
001 1 0 0
101 1 1 0
01 1 1 0 1
1 1 1 1 1 1
FAN5230
REV. 2.8.5 10/17/01 11
3.3V and 5V Under-voltage Protection
When the output voltage of either the 3.3V or 5V falls
below 75% of the nominal value, both converters, go into
under-voltage (UV) protection, after a 2µsec delay. In under-
voltage protection, the high and low side MOSFETs are
turned off. Once under-voltage protection is triggered, it
remains on until power is recycled or the SDWN pin is reset.
12V Architecture
The 12V converter is a traditional non-isolated fly-back (also
known as a "boost" converter). The converter’s input voltage
is the +5V switcher output, so that +12V can only be present
if +5V is present. Also, if the external MOSFET is off, the
output of the +12V converter is +5V, not zero. This in turn
will provide non-zero output for the 12V regulator.
For complete turn-off of the 12V regulator an external
P-channel MOSFET or an LDO regulator with on/off control
may be used. If an LDO is used for 12V then the boost
converter should be set to 13.2V using the external resistor
divider network. If the 12V “boost” converter is not used,
connect VFB12 (pin 15) to 5V-ALWAYS (pin 6).
12V Loop Compensation
The 12V converter should be run in discontinuous conduc-
tion mode. In this mode, the converter will be stable if a
capacitor with suitable ESR value is selected. A 68uF
tantalum with 500mA ripple current rating and 95m is
recommended here.
12V Protection
The 12V converter is protected against overvoltage. If the
12V feedback is more than 10–15% above the nominal set
voltage, a comparator forces the MOSFET off until the volt-
age falls below the comparator threshold.
The 12V converter is also protected against over-current. If a
short circuit pulls the output below 9V, all of the switching
converters go into UV protection, after a 2µs delay. In UV
protection, all MOSFETs are turned off. Once UV protection
is triggered, it remains on until the input power is recycled or
the SDWN is reset.
12V Softstart and Sequencing
The 12V output is started at the same time as the 5V output.
The softly rising 5V output automatically generates a softly
rising 12V output. The duty cycle of the 12V PWM is lim-
ited to prevent excessive current draw.
The 12V supply must build up a voltage higher than the
UVLO limit (9V) by the time the 5V is above its UVLO
(3.75V) in order to avoid triggering of UV protection during
soft start.
5V/3.3V-ALWAYS Operation
The 5V-ALWAYS supply is generated from either the
on-chip linear regulator or through an internal switch from
the VFB pin of the 5V switching supply. The 5V-ALWAYS
supply should be decoupled to ground with a 10µF capacitor.
When the 5V switching supply is off, or if its output voltage
is not within tolerance, the 5V-ALWAYS switch is open, and
the linear regulator is on. When the 5V switching supply is
running and has an output voltage within specification, the
linear regulator is off, and the switch is on. The switch has
sufficiently low resistance that at maximum current draw on
the 5V-ALWAYS supply, the output voltage is regulated
within specifications.
The 3.3V-ALWAYS is generated from a linear regulator
attached internally to the 5V-ALWAYS. The 3.3V-ALWAYS
supply should be decoupled to ground with a 10µF capacitor.
The purpose of the two ALWAYS supplies (combined cur-
rent is specified to never exceed 50mA) is to provide power
to the system micro-controller (8051 class) as well as other
IC’s needing a stand-by power. The micro-controller as well
as the other IC’s could be operated from either 5V or 3.3V
ALWAYS, so the FAN5230 provides both.
5V/3.3V-ALWAYS Protections
The two internal linear regulators are current limited and
under-voltage protected. Once protection is triggered all
outputs are turned off until power is cycled or the SDWN is
reset.
Power good
Power good is asserted when both PWM Buck converters are
above specified threshold. No other regulators are monitored
by Power good. When PGOOD goes low it will stay low for
at least 10µsec (Tw). See fig. 5.
Figure 5. PGOOD Timing Diagram
Vmain
t
PGOOD
t
Vth
Tw
FAN5230
12 REV. 2.8.5 10/17/01
Error Amplier output voltage clamp
During a load transient the error amplifier voltage is allowed
full swing. After two clock cycles, if the amplifier is still out
of range the voltage and consequently the duty cycle (DC) is
clamped. The DC clamp automatically limits the build up of
over-currents during abnormal conditions, including short
circuits:
Figure 6. Duty-Cycle Clamp
Thermal shutdown
If the die temperature of the FAN5230 exceeds safe limits,
the IC shuts itself off. When the over-temperature (OT)
event ends, the IC comes back to normal operation. There is
a 25°C thermal hysteresis between shutdown and start up.
Input UVLO
If the input voltage falls below the UVLO threshold, the
FAN5230 turns itself off and stays off as long as Input
voltage is below threshold.
IC Protections Table
* Only the converter in Over-Voltage goes in SOFT CROW-
BAR mode.
EA
+
VFB=0.5V+Vo/8
VREF
V
RAMP
=0.5V+Vin/8
Vclamp=0.5V+
+Vo/8 +/-0.2V
2 Cycles
Counter
0.4V
+
+
HSD
Buck
LSD
Buck LDO
LSD
Boost
OC/UV
(Bucks)
OFF-LATCH OFF-LATCH ON OFF-LATCH
OC/UV
(LDO)
" " OFF-LATCH "
OV (Buck)*
OFF SOFT
CROWBAR
ON ON
OV (Boost)
ON ON ON OFF
SDWN=0
OFF OFF OFF OFF
OT
OFF OFF OFF OFF
UV (Boost)
OFF-LATCH OFF-LATCH ON OFF-LATCH
OC (Boost)
ON ON ON 33% DC
Generic Mobile System Block Diagram
Figure 7. System Block Diagram
CPU
PGOOD
5V
3.3V
5V-Always
3.3V-
Always
SDN5
SDN3.3
RC5230
RC5231
Vcpu
1.5V
2.5V
µP
Clock
CPU
µC
8051
µC
PGOOD
SDWN
SDWN
Vin=5.6 to 24V
EN
PGOOD
µP CODE EXECUTION
RESET
LOGIC

FAN5230QSCX

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG CONV MOBILE 5OUT 24QSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet