AD1893
REV. A
–15–
80
0
80
24
8
8
16
0
48
32
40
56
64
72
7264564840322416
F
SIN
– kHz
F
SOUT
– kHz
F
SIN
/F
SOUT
= 2/1
F
SIN
/F
SOUT
= 1/1F
SIN
/F
SOUT
= 1/2
6kHz
UP-
SAMPLING
DOWN-
SAMPLING
42kHz
42kHz
Figure 12. Allowable Input and Output Sample Frequencies
F
CRYSTAL
= 12 MHz Case
Multiple SamplePort Synchronization and Performance
Degradation
Multiple parallel AD1893 SamplePorts may be used in a single
system. Multiple AD1893s can be “synchronized” by simply
sharing the same reset and buffered crystal connections (see
Figure 10), and ensuring that all the SamplePorts leave the reset
state on the same crystal falling edge. No other provision is
necessary since the different AD1893s will process samples
identically if they are presented with the same input and output
clocks (neglecting the effect of excessive clock skew on the PCB,
as well process variations between ASRCs which could cause
different devices to trigger at slightly different times on excess-
ively slow rising or falling clock edges).
It is also likely that several AD1893s could end up in a serial
cascade arrangement, either in a single system design or as the
result of two or more systems, each using a single AD1893 in
the signal path. The audio signal quality will be degraded with
each pass through a SamplePort, though to a very minor degree.
The THD+N performance will degrade by 3 dB with every
doubling of the number of passes through an ASRC. For ex-
ample, the AD1893 THD+N specification of –94 dB will rise to
–91 dB if the signal makes two passes through an ASRC. The
overall system THD+N specification will rise to –88 dB with
four passes, and so on.
Clipping
Under certain rare input conditions, it is possible for the
AD1893 to produce a clipped output sample. This situation is
best comprehended by employing the interpolation/decimation
model. If two consecutive samples happened to have full-scale
amplitudes (representing the peak of a full-scale sine wave, for
example), the interpolated sample (or samples) between these
two samples might have an amplitude greater than full scale. As
this is not possible, the AD1893 will compute a full-scale ampli-
tude for the interpolated sample or samples (see Figure 13).
Clipping can also arise due to the pre-echo and post-echo Gibbs
phenomena of the FIR filter, when presented with a full-scale
step input. The result of this erroneous or clipped output
sample may be measured as an extremely small decrease in
headroom for transient signals.
Sample Rate Conversion Ratio Range
The AD1893 does not support exact 1:2 (or 2:1) sample rate
conversion. The SamplePort will convert to within several hertz
of the 1:2 range, but will mute before reaching the exact 1:2
ratio. Thus the AD1893 will not support applications where the
input and output sample clocks are derived from a common
source but differ by a divide-by-two. When the ratio between
the input and output sample clock reaches to within 1% of 1:2
or 2:1, the THD+N performance may degrade by several deci-
bels, due to the wraparound of the internal read/write memory
location pointers.
CORRECTLY INTERPOLATED SAMPLE
CLIPPED INTERPOLATED SAMPLE
FULL-SCALE
AMPLITUDE
TIME
Figure 13. Nipped Output Sample
Options for Sample Rate Conversion over a Wider Range
There are systems requiring sample rate conversion over a range
that is wider than the 1:2 or 2:1 range provided by a single
AD1893, such as for “scrubbing” in digital audio editors. There
are at least two options in this situation. The first is to use a
programmable DSP chip to perform simple integer ratio inter-
polation or decimation, and then use the AD1893 when this
intermediate output sample frequency is within the approximate
1:2 or 2:1 range of the final desired output sample frequency. The
second is to use multiple AD1893 devices cascaded in series to
achieve the required sample rate range.
“Almost Synchronous” Operation
It is possible to apply input and output sample frequencies
which are very close (within a few hertz) or in fact synchronous
(LR_I and LR_O tied together). There is no performance pen-
alty when using the AD1893 in “almost synchronous” applica-
tions. Indeed, there is a very slight performance benefit when
the input and output sample clocks are synchronous since the
alias distortion components which arise from the noninfinite
stopband attenuation of the FIR filter will pile up exactly on top
of the sinusoidal frequency components of the input signal, and
will thus be masked.
It has been empirically observed that during almost synchronous
operation, certain AES/EBU receivers, when used to generate
the input bit clock (BCLK_I) using a 128 times F
S
bit clock
frequency, can suffer sympathetic phase lock to the output bit
clock (BCLK_O) when the output bit clock is also operated at a
128 times F
S
rate. In other words, due to a noise pickup
mechanism in the analog phase lock loop portion of these AES/
EBU receivers, the lock frequency is pulled to match the fre-
quency of the output bit clock. The system can suffer inter-
mittent bursts of audible distortion when this sympathetic lock
phenomenon occurs. Analog Devices recommends avoiding the
use of a 128 times F
S
output bit clock frequency if almost syn-
chronous application is intended. The use of a 64 times F
S
output bit clock rate is recommended.
