AD1893
–6–
REV. A
Output Control Signals
Pin Name DIP LQFP I/O Description
BKPOL_O 19 25 I Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed
on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on
rising.
MODE0_O 18 24 I Serial mode zero control for output port.
MODE1_O 17 21 I Serial mode one control for output port.
MODE0_O MODE1_O
0 0 Left-justified, no MSB delay, LR_O clock triggered.
0 1 Left-justified, MSB delay, LR_O clock triggered.
1 0 Right-justified, MSB delayed 16 bit clock periods from LR_O transition.
1 1 WCLK_O triggered, no MSB delay.
Miscellaneous
Pin Name DIP LQFP I/O Description
XTAL_O 1 40 O Crystal output. Connect to one side of nominal 16 MHz crystal for sampling frequencies
(F
S
word rates) from 8 kHz to 56 kHz.
XTAL_I 2 42 I Crystal input. Connect to other side of nominal 16 MHz crystal for sampling frequencies
(F
S
word rates) from 8 kHz to 56 kHz. Use this input to overdrive the on-chip oscillator
with an external clock source.
RESET 13 14 I Active LO reset. Set HI for normal chip operation.
MUTE_O 16 20 O Mute output. HI indicates that data is not currently valid due to read and write FIFO
memory pointer overlap. LO indicates normal operation.
MUTE_I 15 18 I Mute input. HI mutes the serial output to zeros (midscale). Normally connected to
MUTE_O. Reset LO for normal operation.
SETLSLW 28 38 I Settle slowly to changes in sample rates. HI: Slow-settling mode (800 ms). Less sensitive
to sample clock jitter. LO: Fast-settling mode (200 ms). Some narrow-band noise
modulation may result from jitter on the LR clocks. This signal may be asynchronous with
respect to the crystal frequency, and dynamically changed, but is normally pulled up or
pulled down on a static basis.
PWRDWN 27 36 I Power-down input. Set HI for inactive, low power dissipation state. Reset LO for normal
operation.
NC 9, 20 1, 5, 8, 11, No connect. Reserved. Do not connect.
12, 15, 17,
19, 22, 23,
26, 29, 33,
34, 37, 39,
41, 44
Power Supply Connections
Pin Name DIP LQFP I/O Description
V
DD
7, 22 6, 28 I Positive digital voltage supply.
GND 8, 14, 21 7, 16, 27 I Digital ground. Pin 14 (DIP) and Pin 16 (LQFP) need not be decoupled.
AD1893
REV. A
–7–
THEORY OF OPERATION
There are at least two logically equivalent methods of explaining
the concept of asynchronous sample rate conversion: the high
speed interpolation/decimation model and the polyphase filter
bank model. Using the AD1893 SamplePort does not require
understanding either model. This section is included for those
who wish a deeper understanding of its operation.
Interpolation/Decimation Model
In the high speed interpolation/decimation model, illustrated in
Figure 1, the sampled data input signal (Plot A in Figure 1) is
interpolated at some ratio (IRATIO) by inserting IRATIO-1
zero valued samples between each of the original input signal
samples (Plot B in Figure 1). The frequency domain charac-
teristics of the input signal are unaltered by this operation, ex-
cept that the zero-padded sequence is considered to be sampled
at a frequency which is the product of original sampling fre-
quency multiplied by IRATIO.
The zero-padded values are fed into a digital FIR low-pass filter
(Plot C in Figure 1) to smooth or integrate the sequence, and
limit the bandwidth of the filter output to 20 kHz. The inter-
polated output signal has been quantized to a much finer time
scale than the original sequence. The interpolated sequence is
INPUT
SIGNAL
OUTPUT
SIGNAL
ZERO STUFF
INTERPOLATION
FIR LOW-
PASS
FILTER
ZERO ORDER
HOLD
REGISTER
RESAMPLING
DECIMATION
A
BC
DE
B
C
D
E
A
TIME
AMP
Figure 1. Interpolation/Decimation Model—Time Domain View
then passed to a zero-order hold functional block (physically
implemented as a register, Plot D in Figure 1) and then asyn-
chronously resampled at the output sample frequency (Plot E in
Figure 1). This resampling can be thought of as a decimation
operation since only a very few samples out of the great many
interpolated samples are retained. The output values represent
the “nearest” values, in a temporal sense, produced by the inter-
polation operation. There is always some error in the output
sample amplitude due to the fact that the output sampling switch
does not close at a time that exactly corresponds to a point on the
fine time scale of the interpolated sequence. However, this error
can be made arbitrarily small by using a very large interpolation
ratio. The AD1893 SamplePort ASRC uses an equivalent IRATIO
of 65,536 to provide 16-bit accuracy (–96 dB THD+N) across
the 0 kHz to 20 kHz audio band.
The number of FIR filter taps and associated coefficients is
approximately 4 million. The equivalent FIR filter convolution
frequency (or “upsample” frequency) is 3.2768 GHz, and the
fine time scale has resolution of about 300 ps. Various propri-
etary efficiencies are exploited in the AD1893 ASRC to reduce
the complexity and throughput requirements of the hardware
implied by this interpolation/decimation model.
AD1893
–8–
REV. A
Polyphase Filter Bank Model
Although less intuitively understandable than the interpolation/
decimation model, the polyphase filter bank model is useful to
explore because it more accurately portrays the operation of the
actual AD1893 SamplePort hardware. In the polyphase filter
bank model, the stored FIR filter coefficients are thought of as
the impulse response of a highly oversampled 0 kHz to 20 kHz
low-pass prototype filter, as shown in Figure 2. If this low-pass
filter is oversampled by a factor of N, then it can be conceptu-
ally decomposed into N different “subfilters,” each filter consist-
ing of a different subset of the original set of impulse response
samples. If the temporal position of each of the subfilters is
maintained, then they can be summed to recreate the original
oversampled impulse response. Since the original impulse re-
sponse is highly oversampled, the more sparsely sampled
subfilters still individually meet the Nyquist criterion (i.e., they
AMP
TIME
OVERSAMPLED
LOW-PASS FILTER
IMPULSE RESPONSE
DECOMPOSED INTO
FOUR SUBFILTERS
PHASE
0 Deg
90
180
270
1/4F
S
1/2F
S
3/4F
S
F
S
FREQ
AMP
1/4F
S
1/2F
S
3/4F
S
F
S
1/4F
S
1/2F
S
3/4F
S
F
S
1/4F
S
1/2F
S
3/4F
S
F
S
1/4F
S
1/2F
S
3/4F
S
F
S
Figure 2. Four Polyphase Subfilters in the Time and Frequency Domains
are adequately sampled). The baseband magnitude and phase
responses of the subfilters are identical. The out-of-band (i.e.,
alias) regions of the subfilters however have phase responses
which are shifted relative to one another, in a manner that
causes them to cancel when they are summed.
The subfilter coefficients are then aligned to the left, as shown
in Figure 3, so that the first coefficient of each subfilter is
aligned to the first point on a coarse time scale. (This conceptual
step accounts for how the hardware implementation is able to
operate at the slower rate corresponding to the coarse time
scale.) Each subfilter has been shifted in time by a different
amount, and though they still share identical magnitude re-
sponses, they now have in-band phase responses which have
fractionally different slopes (i.e., group delays).

AD1893JSTZRL

Mfr. #:
Manufacturer:
Description:
Audio Sample Rate Converters IC SamplePort 16-Bit ASRC
Lifecycle:
New from this manufacturer.
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