NCN4557MTR2G

NCN4557
http://onsemi.com
10
18 k
CRD_I/O
14 k
I/O
V
DD
LOGIC
IO/CONTROL
GND
GND
200 ns
200 ns
Q1
Q2
Q3
CRD_V
CC
Figure 10. Basic I/O line Interface
The typical waveform provided in Figure 11 shows how
the accelerator operates. During the first 200 ns (typical),
the slope of the rise time is solely a function of the pullup
resistor associated with the stray capacitance. During this
period, the PMOS devices are not activated since the input
voltage is below their V
gs
threshold. When the input slope
crosses the V
gsth
, the opposite one shot is activated,
providing a low impedance to charge the capacitance, thus
increasing the rise time as depicted in Figure 11. The same
mechanism applies for the opposite side of the line to make
sure the system is optimum.
Figure 11. CRD_IO Typical Rise and Fall Times
with Stray Capacitance > 30 pF
(33 pF capacitor connected on the board)
Powerup Sequence
The powerup sequence makes sure all the card−related
signals are LOW during the CRD_V
CC
positive going
slope. The Powerup sequence is activated by setting the
ENABLE Boolean signal HIGH. CRD_RST, CRD_CLK
and CRD_I/O are maintained LOW during the activation
stage until CRD_V
CC
reaches its nominal value (1.8 V or
3.0 V). Figure 7 shows the typical NCN4557 activation
sequence.
About 800 ms after CRD_V
CC
has reached its nominal
voltage value, CRD_IO and CRD_RST are released.
CRD_CLK is enabled during the rising slope of the
second clock cycle after CRD_IO and CRD_RST are
enabled.
Figure 12. NCN4557 Power−Up
CRD_RSTA/B
CRD_IOA/B
CRD_CLKA/B
CRD_V
CC
A/B
ENABLE
T
ON
~ 0.9 ms
2nd Rise Edge After
CRD_IOA/B Rising
In all cases the application software is responsible for the
smart card signal sequence (contact activation sequence,
cold reset and warm reset sequences).
Powerdown Sequence
The NCN4557 provides a powerdown sequence which is
activated by setting the ENABLE Boolean signal LOW.
The communication I/O session is terminated immediately
according to the ISO7816 and EMV specifications as
depicted in Figures 8 and 13.
ISO7816 Sequence:
CRD_RST is forced to LOW
CRD_CLK is forced to LOW 2 clock cycles after
ENABLE is set LOW unless CRD_CLK is already in
NCN4557
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11
this state or 8 ms after the ENABLE pin is set LOW in
the other cases.
CRD_I/O is forced to LOW about 8 ms after the
ENABLE pin is set LOW.
Then CRD_V
CC
Supply Shuts Off
Figure 13. NCN4557 Power Down Sequence
CRD_V
CC
A/B
CRD_IOA/B
CRD_CLKA/B
CRD_RSTA/B
ENABLE
T
OFF
~ 8.0 ms
Input Schmitt Triggers
All the logic input pins (excepted I/O and CRD_I/O,
Figure 3) have built−in Schmitt trigger circuits to prevent
the NCN4557 against uncontrolled operation. The typical
dynamic characteristics of the related pins are depicted in
Figure 14.
OUTPUT
V
DD
ON
OFF
0.2 x V
DD
or
0.4 V
0.7 x V
DD
INPUT
Figure 14. Typical Schmitt Trigger Characteristics
Shutdown Operating
In order to save power or for other purpose required by
the application it is possible to put the NCN4557 in a
shutdown mode by setting LOW the pin ENABLE. On the
other hand the device enters automatically in a shutdown
mode when V
DD
becomes lower than 1.0 V typically.
ESD Protection
The NCN4557 CRD interface features an Human Body
Model ESD voltage protection in excess of 8 kV for all the
CRD pins (CRD_IOA & B, CRD_CLKA & B,
CRD_RSTA & B, CRD_V
CC
A & B and GND). All the
other pins (microcontroller side) sustain at least 2 kV.
These values are guaranteed for the device in its full
integrity without considering the external capacitors added
to the circuit for a proper operating. Consequently in the
operating conditions it is able to sustain much more than
8 kV on its CRD pins making it perfectly protected against
electrostatic discharge well over the Human Body Model
ESD voltages required by the ISO7816 standard (4 kV).
Printed Circuit Board Layout
Careful layout routing will be applied to achieve a good
and efficient operating of the device in its mobile or
portable environment and fully exploit its performance.
The bypass capacitors have to be connected as close as
possible to the device pins (CRD_V
CC
A and B, V
DD
or
V
BAT
) in order to reduce as much as possible parasitic
behaviors (ripple and noise). It is recommended to use
ceramic capacitors.
The exposed pad of the QFN−16 package will be
connected to the ground. A relatively large ground plane is
recommended.
ORDERING INFORMATION
Device Package Shipping
NCN4557MTG QFN−16
(Pb−Free)
123 Units / Rail
NCN4557MTR2G QFN−16
(Pb−Free)
3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCN4557
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12
PACKAGE DIMENSIONS
QFN16 3*3*0.75 MM, 0.5 P
CASE 488AK−01
ISSUE O
16X
SEATING
PLANE
L
D
E
0.15 C
A
A1
e
D2
E2
b
1
4
58
12
9
16 13
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. L
max
CONDITION CAN NOT VIOLATE 0.2 MM
SPACING BETWEEN LEAD TIP AND FLAG.
B
A
0.15 C
TOP VIEW
SIDE VIEW
BOTTOM VIEW
PIN 1
LOCATION
0.10 C
0.08 C
(A3)
C
16 X
16X
NOTE 5
0.10 C
0.05 C
A B
NOTE 3
K16X
EXPOSED PAD
DIM MIN MAX
MILLIMETERS
A 0.70 0.80
A1 0.00 0.05
A3 0.20 REF
b 0.18 0.30
D 3.00 BSC
D2 1.65 1.85
E 3.00 BSC
E2 1.65 1.85
e 0.50 BSC
K 0.20 −−−
L 0.30 0.50
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Phone: 81−3−5773−3850
NCN4557/D
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NCN4557MTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Translation - Voltage Levels ANA DUAL SMART CARD INT
Lifecycle:
New from this manufacturer.
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