NCN4557
http://onsemi.com
4
PIN DESCRIPTIONS
PIN Name Type Description
1 CRD_V
CC
B POWER This pin is connected to the Card power supply pin (C1) (Card B).The corresponding LDO is
programmable using the pins SEL0, SEL1 and ENABLE to provide 1.8 V, 3.0 V or 0 V (disable).
CRD_V
CC
B can not be active when CRD_V
CC
A is active and conversely.
2 V
DD
POWER This pin is connected to the controller power supply. It configures the level shifter input stage to accept
the signal coming from the microcontroller. A 0.1 mF capacitor shall be used to bypass the power supply
voltage. When V
DD
is below 1.5 V typical CRD_V
CC
A and B are disabled; the NCN4557 comes into a
shutdown mode.
3 V
BAT
POWER DC/DC converter power supply input shared by the LDOs A & B. This pin has to be bypassed by a
0.1 mF capacitor.
4 CRD_V
CC
A POWER This pin is connected to the Card power supply pin (C1) (Card A).The corresponding LDO is
programmable using the pins SEL0, SEL1 and ENABLE to provide 1.8 V, 3.0 V or 0 V (disable).
CRD_V
CC
A can not be active when CRD_V
CC
B is active and conversely.
5 CRD_CLKA OUTPUT This pin is connected to the clock pin (C3) of the card connector A. The clock (CLK) signal comes from
the external clock generator (standalone clock source or microcontroller). The internal level shifter
adapts the voltage levels CLK to CRD_CLKA. An internal active pull− down NMOS device maintains this
pin to Ground during either the CRD_V
CC
A start−up sequence, or when CRD_V
CC
A = 0 V.
6 CRD_RSTA OUTPUT This pin is connected to the RESET pin (C2) of the card connector A. A level translator adapts the
RESET signal from the microcontroller to the external card A. The output current is internally limited to
15 mA max. Similarly to the CRD_CLK A or B pins this pin is maintained Low when CRD_V
CC
A = 0 V
and during the corresponding LDO transient phase of power−up.
7 CRD_I/OA INPUT /
OUTPUT
This pin handles the connection to the serial I/O pin (C7) of the card connector A. A bidirectional level
translator adapts the serial I/O signal between the card and the micro−controller. A 14 kW (typical)
pull−up resistor provides a High Impedance state to the card I/O link; during the operating phase, a
dynamic pull−up circuit is activated making the CRD_I/OA rise time compliant with the ISO7816, EMV,
GSM and related standards. An internal active pull−down MOS device forces this pin to Ground during
either the CRD_V
CC
A start−up sequence or when CRD_V
CC
A = 0 V. The CRD_I/OA pin is internally
limited by a 15 mA max current.
8 I/O INPUT /
OUTPUT
This pin is connected to an external microcontroller or cellular phone management unit (Baseband circuit
or PMU). A bidirectional level translator adapts the serial I/O signal between the smart card A or B and
the controller. Only one card, the selected card, communicates through the bidirectional I/O interface. A
built−in 18 kW typical resistor provides a high impedance state when the interface is not activated. An
additional dynamic pullup circuit accelerates the I/O rise time making the bidirectional channel perfectly
balanced in regards to the standard rise time requirements.
9 RST INPUT The RESET signal present at this pin is connected to the card through the internal level shifter which
translates the levels according to the CRD_V
CC
A or B programmed value.
10 CLK INPUT The clock signal, coming from the external controller, must have a Duty Cycle within the Min/Max values
defined by the specification (typically 50%). The built−in level shifter translates the input signal to the
external card CLK input.
11 SEL1 INPUT SEL1 allows the selection of the Card A or B (Table 1).
SEL1 = Low ! Card A selected
SEL1 = High ! Card B selected
12 SEL0 INPUT SEL0 allows programming CRD_V
CC
A or B (1.8 V or 3.0 V) (Table 1).
SEL0 = Low ! CRD_V
CC
A/B = 1.8 V
SEL0 = High ! CRD_V
CC
A/B = 3.0 V
13 ENABLE INPUT Power Up and Down pin:
ENABLE = Low ! Low current shutdown mode activated
ENABLE = High ! Normal Operation
A Low level on this pin switches off the card interface.
14 CRD_I/OB INPUT /
OUTPUT
This pin handles the connection to the serial I/O pin (C7) of the card connector B. A bidirectional level
translator adapts the serial I/O signal between the card and the micro−controller. A 14 kW (typical)
pull−up resistor provides a High Impedance state to the card I/O link; during the operating phase a
dynamic pull−up circuit is activated making the CRD_I/OB rise time compliant with the ISO7816, EMV,
GSM and related standards. An internal active pulldown MOS device forces this pin to Ground during
either the CRD_V
CC
B start−up sequence or when CRD_V
CC
B = 0 V. The CRD_I/OB pin is internally
limited by a 15 mA maximum current.
15 CRD_RSTB OUTPUT This pin is connected to the RESET pin of the card connector B. A level translator adapts the RESET
signal from the microcontroller to the external card B. The output current is internally limited by a 15 mA
max current. Similarly to the CRD_CLK A or B pins this pin is maintained Low when CRD_V
CC
B = 0 V
and during the corresponding LDO transient phase of powerup.
16 CRD_CLKB OUTPUT This pin is connected to the clock pin (C3) of the card connector B. The clock (CLK) signal comes from
the external clock generator (standalone clock source or microcontroller). The internal level shifter
adapts the voltage levels CLK to CRD_CLKB. An internal active pull down NMOS device maintains this
pin to Ground during either the CRD_V
CC
B start−up sequence, or when CRD_V
CC
B = 0 V.
17 GND GND This pin number is the Exposed Pad which is the electrical Ground of the device. It must be soldered to
the PCB ground plane.
