1. General description
The GTL2018 is an octal translating transceiver designed for 3.3 V LVTTL system
interface with a GTL/GTL/GTL+ bus.
The direction pin (DIR) allows the part to function as either a GTL-to-LVTTL sampling
receiver or as an LVTTL-to-GTL interface.
The GTL2018 LVTTL inputs (only) are tolerant up to 5.5 V, allowing direct access to TTL
or 5 V CMOS inputs.
2. Features and benefits
Operates as an octal GTL/GTL/GTL+ sampling receiver or as an LVTTL to
GTL/GTL/GTL+ driver
3.0 V to 3.6 V operation with 5 V tolerant LVTTL input
GTL input and output 3.6 V tolerant
V
ref
adjustable from 0.5 V to 0.5V
CC
Partial power-down permitted
Latch-up protection exceeds 100 mA per JESD78
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-CC101
AEC-Q100 compliance available
Package offered: TSSOP24
3. Quick reference data
GTL2018
8-bit LVTTL to GTL transceiver
Rev. 2 — 29 August 2011 Product data sheet
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
C
i
input capacitance control inputs;
V
I
=3.0Vor0V
-22.5pF
C
io
input/output capacitance A port; V
O
=3.0Vor0V - 4.6 6 pF
B port; V
O
=V
TT
or 0 V - 3.4 4.3 pF
GTL; V
ref
= 0.8 V; V
TT
=1.2V
t
PLH
LOW to HIGH propagation delay An to Bn; see Figure 3 -2.85ns
t
PHL
HIGH to LOW propagation delay An to Bn; see Figure 3 -3.47ns
t
PLH
LOW to HIGH propagation delay Bn to An; see Figure 4 -5.28ns
t
PHL
HIGH to LOW propagation delay Bn to An; see Figure 4 -4.97ns
