GTL2018 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 August 2011 7 of 16
NXP Semiconductors
GTL2018
8-bit LVTTL to GTL transceiver
11. Dynamic characteristics
[1] All typical values are at V
CC
= 3.3 V and T
amb
=25C.
11.1 Waveforms
V
M
= 1.5 V at V
CC
3.0 V; V
M
=0.5V
CC
at V
CC
2.7 V for A ports and control pins;
V
M
=V
ref
for B ports.
Table 8. Dynamic characteristics
V
CC
=3.3V
0.3 V.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
GTL; V
ref
= 0.6 V; V
TT
=0.9V
t
PLH
LOW to HIGH propagation delay An to Bn; see Figure 3 -2.85ns
t
PHL
HIGH to LOW propagation delay An to Bn; see Figure 3 -3.37ns
t
PLH
LOW to HIGH propagation delay Bn to An; see Figure 4 -5.38ns
t
PHL
HIGH to LOW propagation delay Bn to An; see Figure 4 -5.28ns
GTL; V
ref
= 0.8 V; V
TT
=1.2V
t
PLH
LOW to HIGH propagation delay An to Bn; see Figure 3 -2.85ns
t
PHL
HIGH to LOW propagation delay An to Bn; see Figure 3 -3.47ns
t
PLH
LOW to HIGH propagation delay Bn to An; see Figure 4 -5.28ns
t
PHL
HIGH to LOW propagation delay Bn to An; see Figure 4 -4.97ns
GTL+; V
ref
= 1.0 V; V
TT
=1.5V
t
PLH
LOW to HIGH propagation delay An to Bn; see Figure 3 -2.85ns
t
PHL
HIGH to LOW propagation delay An to Bn; see Figure 3 -3.47ns
t
PLH
LOW to HIGH propagation delay Bn to An; see Figure 4 -5.18ns
t
PHL
HIGH to LOW propagation delay Bn to An; see Figure 4 -4.77ns
V
M
= 1.5 V for A port and V
ref
for B port A port to B port
a. Pulse duration b. Propagation delay times
Fig 3. Voltage waveforms
002aab140
3.0 V
0 V
t
p
V
M
V
M
002aab141
3.0 V
0 V
V
OH
V
OL
t
PLH
t
PHL
V
ref
V
ref
1.5 V 1.5 Vinput
output
GTL2018 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 August 2011 8 of 16
NXP Semiconductors
GTL2018
8-bit LVTTL to GTL transceiver
12. Test information
PRR 10 MHz; Z
o
=50; t
r
2.5 ns; t
f
2.5 ns
Fig 4. Propagation delay, Bn to An
002aab142
V
TT
1
/
3
V
TT
V
OH
V
OL
t
PLH
t
PHL
1.5 V1.5 V
V
ref
V
ref
input
output
Fig 5. Load circuitry for switching times
R
L
= load resistor.
C
L
= load capacitance; includes jib and probe capacitance.
R
T
= termination resistance; should be equal to Z
o
of pulse generators.
Fig 6. Load circuit for B outputs
PULSE
GENERATOR
V
O
C
L
50 pF
002aab006
R
L
500 Ω
R
T
V
I
V
CC
DUT
GTL2018 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 2 — 29 August 2011 9 of 16
NXP Semiconductors
GTL2018
8-bit LVTTL to GTL transceiver
13. Package outline
Fig 7. Package outline SOT355-1 (TSSOP24)
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
0.4
0.3
8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT355-1 MO-153
99-12-27
03-02-19
0.25
0.5
0.2
w M
b
p
Z
e
112
24
13
pin 1 index
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
D
y
0 2.5 5 mm
scale
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
A
max.
1.1

GTL2018PW,118

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Bus Transceivers 4-BIT BI-DIREC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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