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MK2069-01GILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
DATASHEET
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER MK2069-01
IDT®
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER 1
MK2069-01 REV K 051310
Description
The MK2069-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that offers system
synchronization, jitter attenuation, and frequency
multiplication or translation. It can accept an unstable, jittery
input clock and provide a de-jittered, low phase noise
output clock at a user determined frequency. The device’s
clock multiplication ratios are user selectable since all major
PLL divider blocks can be configured through device pin
settings. External PLL loop filter components allow tailoring
of the VCXO PLL loop response and therefore the clock
jitter attenuation characteristics.
The MK2069-01 is ideal for line card applications. Its three
input MUX enables selection of the master or slave
(backup) system clocks, as well as a backup local line card
clock. The lock detector (LD) output serves as a clock
status monitor. The clear (CLR
) input enables rapid
synchronization to the phase of a newly selected input
clock, while eliminating the generation of extra clock cycles
and wander caused by memory in the PLL feedback divider.
CLR
also serves as a temporary holdover function when
kept low.
Features
• Input clock frequency of 1 kHz to 170 MHz
• Output clock frequency of 500 kHz to 160 MHz
• Jitter attenuation of input clock provided by VCXO circuit.
Jitter transfer characteristics user configured through
selection of external loop filter components.
• 3:1 Input MUX for input reference clocks
• PLL lock status output
• PLL Clear function allows seamless synchronizing to an
altered input clock phase, virtually eliminating the
generation of wander or extra clock cycles.
• VCXO-based clock generation offers very low jitter and
phase noise generation, even with a low frequency or
jittery input clock.
• 2nd PLL provides translation of VCXO PLL output
(VCLK) to higher or alternate clock frequencies (TCLK).
• Device will free-run in the absence of an input clock
based on the VCXO crystal frequency.
• 56 pin TSSOP package
• Single 3.3 V power supply
• 5 V tolerant inputs on ICLK0 and ICLK1
Block Diagram
Charge
Pump
VCXO
Pullable
xtal
VCLK
X2X1
ISET
4
VDD
4
CLR
LF
FV Divider
1-4096
RV
Divider
1,2,4,128
SV
Divider
1,2,4,6,8,
10,12,16
ICLK2
ICLK1
MX1:0
0X
RV1:0
2
RT
Divider
1-4
Phase
Detector
VCXO
PLL
FT Divider
1-64
ST
Divider
2,4,8,16
VCO
Translator
PLL
SV2:0
3
FV11:0 FT5:0
6
ST1:0
2
TCLK
OEV
OET
ICLK0
10
01
2
LD
OEL
GND
RCLK
OER
Lock Detector
12
LDC LDR
LFR
RT1:0
2
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER VCXO AND SYNTHESIZER
IDT®
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER 2
MK2069-01 REV K 051310
Pin Assignment
Input Selection Tables
Input Mux Selection Table
VCXO PLL Reference Divider Selection Table
VCXO PLL Feedback Divider Selection
VCXO PLL Scaling Divider Selection Table
Translator PLL Reference Divider Selection Table
Translator PLL Feedback Divider Selection
Translator PLL Scaling Divider Selection Table
MX1 MX0 Input Selection
00 ICLK0
01 ICLK0
10 ICLK1
11 ICLK2
RV1 RV0 RV Divider Ratio
00 4
01 128
10 2
11 1
21FV0
22
FV1
23
FV2
24
FV3
1ST0
2
ST1
3
RT0
4
RT1
5
FT0
6
FT1
7
FT2
8
FT3
9
FT4
10
FT5
11
RV0
12
VDDT
13
GNDT
14
X1
15
VDDV
16
X2
17
GNDV
18
LFR
19
LF
20
ISET
25
FV4
26
FV5
27
FV6
28
FV7
36
35
34
33
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
32
31
30
29
CLR
ICLK0
ICLK2
MX1
SV2
SV1
SV0
RV1
MX0
ICLK1
OEL
OET
OEV
OER
VDD
LD
TCLK
VDDP
VCLK
GNDP
RCLK
LDR
GND
LDC
FV11
FV10
FV9
FV8
MK2069-01
FV11:0 FV Divider Ratio Notes
0...00 2
For FV addresses 0 to 4094,
FV Divide = Address + 2
0...01 3
::
1...10 4096
1...11 1
SV2 SV1 SV0 SV Divider Ratio
000 4
001 6
010 8
011 10
100 12
101 2
110 16
111 1
RT1 RT0 RT Divider Ratio
00 2
01 3
10 4
11 1
FT5:0 FT Divider
Ratio
Notes
000000 2
For FT addresses 0 to 62,
FT Divide = Address + 2
000001 3
::
111110 64
111111 1
ST1 ST0 ST Divider Ratio
00 2
01 4
10 8
11 16
MK2069-01
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER VCXO AND SYNTHESIZER
IDT®
VCXO-BASED LINE CARD CLOCK SYNCHRONIZER 3
MK2069-01 REV K 051310
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 ST0 Input Scaling Divider bit 0 input, Translator PLL (internal pull-up).
2 ST1 Input Scaling Divider bit 1 input, Translator PLL (internal pull-up).
3 RT0 Input Reference Divider bit 0 input, Translator PLL (internal pull-up).
4 RT1 Input Reference Divider bit 1 input, Translator PLL (internal pull-up).
5 FT0 Input Feedback Divider bit 0 input, Translator PLL (internal pull-up).
6 FT1 Input Feedback Divider bit 1 input, Translator PLL (internal pull-up).
7 FT2 Input Feedback Divider bit 2 input, Translator PLL (internal pull-up).
8 FT3 Input Feedback Divider bit 3 input, Translator PLL (internal pull-up).
9 FT4 Input Feedback Divider bit 4 input, Translator PLL (internal pull-up).
10 FT5 Input Feedback Divider bit 5 input, Translator PLL (internal pull-up).
11 RV0 Input Reference Divider bit 0 input, VCXO PLL (internal pull-up).
12 VDDT Power Power Supply connection for translator PLL.
13 GNDT Ground Ground connection for translator PLL.
14 X1 - Crystal oscillator input. Connect this pin to the external reference crystal.
15 VDDV Power Power Supply connection for VCXO PLL.
16 X2 - Crystal oscillator output. Connect this pin to the external reference crystal.
17 GNDV Ground Ground connection for VCXO PLL.
18 LFR - Loop filter connection, reference node. Refer to loop filter circuit on page 6.
19 LF - Loop filter connection, active node. Refer to loop filter circuit on page 6.
20 ISET - Charge pump current setting input. Refer to loop filter circuit on page 6.
21 FV0 Input Feedback Divider bit 0 input, VCXO PLL (internal pull-up).
22 FV1 Input Feedback Divider bit 1 input, VCXO PLL (internal pull-up).
23 FV2 Input Feedback Divider bit 2 input, VCXO PLL (internal pull-up).
24 FV3 Input Feedback Divider bit 3 input, VCXO PLL (internal pull-up).
25 FV4 Input Feedback Divider bit 4 input, VCXO PLL (internal pull-up).
26 FV5 Input Feedback Divider bit 5 input, VCXO PLL (internal pull-up).
27 FV6 Input Feedback Divider bit 6 input, VCXO PLL (internal pull-up).
28 FV7 Input Feedback Divider bit 7 input, VCXO PLL (internal pull-up).
29 FV8 Input Feedback Divider bit 8 input, VCXO PLL (internal pull-up).
30 FV9 Input Feedback Divider bit 9 input, VCXO PLL (internal pull-up).
31 FV10 Input Feedback Divider bit 10 input, VCXO PLL (internal pull-up).
32 FV11 Input Feedback Divider bit 11 input, VCXO PLL (internal pull-up).
33 MX1 Input Input MUX selection bit 1 (internal pull-up).
34 ICLK2 Input Reference clock input 2.
35 ICLK0 Input Reference clock input 0. 5V tolerant input.
36 CLR
Input Clear input, clears VCXO PLL dividers when low (internal pull-up).
37 LDC - Lock detector threshold setting circuit connection. Refer to circuit on page 10.
38 GND Ground Digital ground connection.
39 LDR - Lock detector threshold setting circuit connection. Refer to circuit on page 10.
40 RCLK Output VCXO PLL phase detector Reference Clock output.
41 GNDP Ground Ground connection for output drivers (VCLK, TCLK, RCLK, LD, LDR).
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

MK2069-01GILF

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Description:
Clock Synthesizer / Jitter Cleaner VCXO-BASED LINE CARD CLOCK SYNCHRONIZER
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