MK2069-01GILF Datasheet MK2069-01GILFTR, MK2069-01GILF | P10-P12

MK2069-01

VCXO-BASED LINE CARD CLOCK SYNCHRONIZER VCXO AND SYNTHESIZER

IDT®

VCXO-BASED LINE CARD CLOCK SYNCHRONIZER 10

MK2069-01 REV K 051310

previously selected input. The phase compensation circuit

allows the VCXO PLL to quickly lock to the new input phase

without producing extra clock cycles or clock wander,

assuming the new clock is at the same frequency.

Input pin CLR

controls the phase compensation circuit. CLR

must remain high for normal operation. When used in

conjunction with the input MUX select pins, CLR

should be

brought low prior to MUX reselection, then returned high

after MUX reselection. This prevents the VCXO PLL from

attempting to lock to the new input clock phase associated

with the input clock.

When CLR

is high, the VCXO PLL operates normally.

When CLR

is low, the VCXO PLL charge pump output is

inactivated which means that no charge pump correction

pulses are provided to the loop filter. During this time, the

VCXO frequency is held constant by the residual charge or

voltage on the PLL loop filter, regardless of the input clock

condition. However, the VCXO frequency will drift over time,

eventually to the minimum pull range of the crystal, due to

leak-off of the loop filter charge. This means that CLR

can

provide a holdover function, but only for a very short

duration, typically in milliseconds.

Upon bringing CLR

high, the FV Divider is reset and begins

counting upon with the first positive edge of the new input

clock, and the charge pump is re-activated. By resetting the

FV Divider, the memory of the previous input clock phase is

removed from the feedback divider, eliminating the

generation of extra VCLK clock cycle that would occur if the

loop was to re-lock under normal means. Lock time is also

reduced, as is the generation of clock wander.

By using CLR

in this fashion VCLK will align to the input

clock phase with only one or two VCLK cycle slips resulting.

When CLR

is not used, the number of VCLK cycle slips can

be as high the FV Divider value.

TCLK is always locked to VCLK regardless of the state of

the CLR

input.

Lock Detection

The MK2069-01 includes a lock detection feature that

indicates lock status of VCLK relative to the selected input

reference clock. When phase lock is achieved (such as

following power-up), the LD output goes high. When phase

lock is lost (such as when the input clock stops, drifts beyond

the pullable range of the crystal, or suddenly shifts in

phase), the LD output goes low.

The definition of a “locked” condition is determined by the

user. LD is high when the VCXO PLL phase detector error

is below the user-defined threshold. This threshold is set by

external components RLD and CLD shown in the Lock

Detection Circuit Diagram, below.

To help guard against false lock indications, the LD pin will

go high only when the phase error is below the set threshold

for 8 consecutive phase detector cycles. The LD pin will go

low when the phase error is above the set threshold for only

1 phase detector cycle.

The lock detector threshold (phase error) is determined by

the following relationship:

(LD Threshold) = 0.6 x R x C

Where:

1 kΩ < R < 1 MΩ (to avoid excessive noise or leakage)

C > 50 pF (to avoid excessive error due to stray

capacitance, which can be as much as 10 pF

including Cin of LDC)

Lock Detector Application example:

The desired maximum allowable loop phase error for a

generated 19.44MHz clock is 100UI which is 5.1 μs.

Solution: 5.1 μs = (0.001 μF) x (8.5 kΩ)

Under ideal conditions, where the VCXO is phase- locked to

a low-jitter reference input, loop phase error is typically

maintained to within a few nanoseconds.

MK2069-01

VCXO-BASED LINE CARD CLOCK SYNCHRONIZER VCXO AND SYNTHESIZER

IDT®

VCXO-BASED LINE CARD CLOCK SYNCHRONIZER 11

MK2069-01 REV K 051310

Lock Detection Circuit Diagram

If the lock detection circuit is not used, the LDR output may

remain unconnected, however the LDC input should be tied

high or low. If the PCB was designed to accommodate the

RLD and CLD components but the LD output will not be

used, RLD can remain unstuffed and CLD can be replaced

with a resistor (< 10 kohm).

Power Supply Considerations

As with any integrated clock device, the MK2069-01 has a

special set of power supply requirements:

• The feed from the system power supply must be filtered

for noise that can cause output clock jitter. Power supply

noise sources include the system switching power supply

or other system components. The noise can interfere with

device PLL components such as the VCO or phase

detector.

• Each VDD pin must be decoupled individually to prevent

power supply noise generated by one device circuit block

from interfering with another circuit block.

• Clock noise from device VDD pins must not get onto the

PCB power plane or system EMI problems may result.

This above set of requirements is served by the circuit

illustrated in the Recommended Power Supply Connection

(next page). The main features of this circuit are as follows:

• Only one connection is made to the PCB power plane.

• The capacitors and ferrite chip (or ferrite bead) on the

common device supply form a lowpass ‘pi’ filter that

remove noise from the power supply as well as clock

noise back toward the supply. The bulk capacitor should

be a tantalum type, 1 μF minimum. The other capacitors

should be ceramic type.

• The power supply traces to the individual VDD pins

should fan out at the common supply filter to reduce

interaction between the device circuit blocks.

• The decoupling capacitors at the VDD pins should be

ceramic type and should be as close to the VDD pin as

possible. There should be no via’s between the

decoupling capacitor and the supply pin.

Recommended Power Supply Connection

Series Termination Resistor

Output clock PCB traces over 1 inch should use series

termination to maintain clock signal integrity and to reduce

EMI. To series terminate a 50Ω trace, which is a commonly

used PCB trace impedance, place a 33Ω resistor in series

with the clock line as close to the clock output pin as

possible. The nominal impedance of the clock output is 20Ω.

Lock Detection Circuit

Lock

Qualification

Counter

(8 up, 1 down)

VCXO

Phase

Detector

Error

Output

LDCLDR

RLD

CLD

RESET

Divider

Output

OEL

Input Threshold

set to VDD/2

Connection Via to 3.3V

Power Plane

Ferrite

Chip

0.1 µF

BULK

1 nF

VDD

0.01 µF

VDD

0.01 µF

VDD

0.01 µF

VDD

0.01 µF

MK2069-01

VCXO-BASED LINE CARD CLOCK SYNCHRONIZER VCXO AND SYNTHESIZER

IDT®

VCXO-BASED LINE CARD CLOCK SYNCHRONIZER 12

MK2069-01 REV K 051310

Quartz Crystal

The MK2069-01 operates by phase-locking the VCXO

circuit to the input signal at the selected ICLK input. The

VCXO consists of the external crystal and the integrated

VCXO oscillator circuit. To achieve the best performance

and reliability, a crystal device with the recommended

parameters must be used, and the layout guidelines

discussed in the following section must be followed.

The frequency of oscillation of a quartz crystal is determined

by its cut and by the load capacitors connected to it. The

MK2069-01 incorporates variable load capacitors on-chip

which “pull” or change the frequency of the crystal. The

crystals specified for use with the MK2069-01 are designed

to have zero frequency error when the total of on-chip +

stray capacitance is 14pF. To achieve this, the layout should

use short traces between the MK2069-01 and the crystal.

Recommended Crystal Parameters:

Crystal parameters can be found in application note MAN05

on www.idt.com

. Approved crystals can be found at

www.idt.com

(search “crystal”).

Crystal Tuning Load Capacitors

The crystal traces should include pads for small capacitors

from X1 and X2 to ground, shown as C

in the External

VCXO PLL Components diagram on page 6. These

capacitors are used to center the total load capacitor

adjustment range imposed on the crystal. The load

adjustment range includes stray PCB capacitance that

varies with board layout. Because the typical telecom

reference frequency is accurate to less than 32 ppm, the

MK2069-01 may operate properly without these adjustment

capacitors. However, IDT recommends that these

capacitors be included to minimize the effects of variation in

individual crystals, including those induced by temperature

and aging. The value of these capacitors (typically 0-4 pF)

is determined once for a given board layout, using the

procedure described in MAN05

PCB Layout Recommendations

For optimum device performance and lowest output phase

noise, the following guidelines should be observed. Please

refer to the Recommended PCB Layout drawing on the

following page.

1) Each 0.01µF decoupling capacitor (CD) should be

mounted on the component side of the board as close to the

VDD pin as possible. No via’s should be used between the

decoupling capacitor and VDD pin. The PCB trace to VDD

pin should be kept as short as possible, as should the PCB

trace to the ground via. Distance of the ferrite chip and bulk

decoupling from the device is less critical.

2) The loop filter components must also be placed close to

the CHGP and VIN pins. C

should be closest to the device.

Coupling of noise from other system signal traces should be

minimized by keeping traces short and away from active

signal traces. Use of vias should be avoided.

3) The external crystal should be mounted as close to the

device as possible, on the component side of the board.

This will keep the crystal PCB traces short which will

minimize parasitic load capacitance on the crystal and as

well as noise pickup. The crystal traces should be spaced

away from each other and should use minimum trace width.

There should be no signal traces near the crystal or the

traces. Also refer to the Optional Crystal Shielding section

that follows.

4) To minimize EMI the 33Ω series termination resistor, if

needed, should be placed close to the clock output.

5) All components should be on the same side of the board,

minimizing vias through other signal layers (the ferrite bead

and bulk decoupling capacitor may be mounted on the

back). Other signal traces should be routed away from the

MK2069-01. This includes signal traces on PCB traces just

underneath the device, or on layers adjacent to the ground

plane layer used by the device.

6) Because each input selection pin includes an internal

pull-up device, those inputs requiring a logic high state (“1”)

can be left unconnected. The pins requiring a logic low state

(“0”) can be grounded.

Optional Crystal Shielding

The crystal and connection traces to pins X1 and X2 are

sensitive to noise pickup. In applications that are especially

sensitive to noise, such as SONET or G-Bit ethernet

transceivers, some or all of the following crystal shielding

techniques should be considered. This is especially

important when the MK2069-01 is placed near high speed

logic or signal traces.

The following techniques are illustrated on the

Recommended PCB Layout drawing.

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