OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

NBSG11MNR2G

P1-P3P4-P6P7-P9P10-P11
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 17
1 Publication Order Number:
NBSG11/D
NBSG11
2.5V/3.3V SiGe 1:2
Differential Clock Driver
with RSECL* Outputs
*Reduced Swing ECL
Description
The NBSG11 is a 1−to−2 differential fanout buffer, optimized for
low skew and Ultra−Low JITTER.
Inputs incorporate internal 50 W termination resistors and accept
Negative ECL (NECL), Positive ECL (PECL), CML, LVCMOS,
LVTTL, or LVDS. Outputs are Reduced Swing ECL (RSECL),
400 mV. All outputs loaded with 50 W to V
CC
− 2 V.
Features
• Maximum Input Clock Frequency up to 12 GHz Typical
• Maximum Input Data Rate up to 12 Gb/s Typical
• 30 ps Typical Rise and Fall Times
• 125 ps Typical Propagation Delay
• RSPECL Output with Operating Range: V
CC
= 2.375 V to 3.465 V
with V
EE
= 0 V
• RSNECL Output with RSNECL or NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
• RSECL Output Level (400 mV Peak−to−Peak Output), Differential
Output Only
• 50 W Internal Input Termination Resistors
• Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices
• These are Pb−Free Devices
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
MARKING DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
16
SG
11
ALYWG
G
1
1
NBSG11
http://onsemi.com
2
V
EE
NC NC V
CC
V
EE
NC NC V
CC
Q0
Q0
Q1
Q1
VTCLK
CLK
CLK
VTCLK
5678
16 15 14 13
12
11
10
9
1
2
3
4
NBSG11
Exposed Pad (EP)
Figure 1. QFN16 Pinout (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 VTCLK −
Internal 50 W Termination Pin. See Table 2.
2 CLK ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Internal 75 kW to V
EE
and 36.5 kW to V
CC
.
3 CLK ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Internal 75 kW to V
EE
.
4 VTCLK −
Internal 50 W Termination Pin. See Table 2.
5,16 V
EE
− Negative Supply Voltage
6,7,14,15 NC − No Connect
8,13 V
CC
− Positive Supply Voltage
9 Q1 RSECL Output
Inverted Differential Output 1. Typically Terminated with 50 W to V
TT
= V
CC
− 2.0 V.
10 Q1 RSECL Output
Noninverted Differential Output 1. Typically Terminated with 50 W to V
TT
= V
CC
− 2.0 V.
11 Q0 RSECL Output
Inverted Differential output 0. Typically Terminated with 50 W to V
TT
= V
CC
− 2.0 V.
12 Q0 RSECL Output
Noninverted Differential Output 0. Typically Terminated with 50 W to V
TT
= V
CC
− 2.0 V.
− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is not electrically connected to the die but may be electrically
and thermally connected to V
EE
on the PC board.
1. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad on package
bottom (see case drawing) must be attached to a heat−sinking conduit.
2. In the differential configuration when the input termination pins (VTCLK, VTCLK
) are connected to a common termination voltage, and
if no signal is applied then the device will be susceptible to self−oscillation.
NBSG11
http://onsemi.com
3
50 W
50 W
VTCLK
CLK
CLK
VTCLK
V
EE
V
CC
Figure 2. Logic Diagram
75 KW 75 KW
36.5 KW
Q1
Q1
Q0
Q0
Table 2. INTERFACING OPTIONS
INTERFACING OPTIONS CONNECTIONS
CML Connect VTCLK and VTCLK to V
CC
LVDS Connect VTCLK and VTCLK together
AC−COUPLED Bias VTCLK and VTCLK Inputs within
(VIHCMR) Common Mode Range
RSECL, PECL, NECL Standard ECL Termination Techniques
LVTTL, LVCMOS An external voltage should be be applied to the
unused complementary differential input.
Nominal voltage is 1.5 V for LVTTL and V
CC
/2
for LVCMOS inputs.
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor (CLK, CLK)
75 kW
Internal Input Pullup Resistor (CLK)
36.5 kW
ESD Protection Human Body Model
Machine Model
> 2 kV
> 100 V
Moisture Sensitivity (Note 3) Pb−Free Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count 125
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
P1-P3P4-P6P7-P9P10-P11

NBSG11MNR2G

Mfr. #:
Buy NBSG11MNR2G
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V SiGE 1:2 Diff Clock w/RSECL
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet