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7
Table 7. DC CHARACTERISTICS, NECL or RSNECL INPUT WITH NECL OUTPUT V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V
(Note 17)
Symbo
l
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
POWER SUPPLY CURRENT
I
EE
Negative Power Supply Current 45 60 75 45 60 75 45 60 75 mA
RSPECL OUTPUTS (Note 18)
V
OH
Output HIGH Voltage −1050 −970 −925 −975 −935 −900 −950 −910 −875 mV
V
OUTPP
Output Voltage Amplitude 350 410 525 350 410 525 350 410 525 mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE−ENDED (Figures 4 & 6) (Note 19)
V
IH
Input HIGH Voltage V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
mV
V
IL
Input LOW Voltage V
EE
V
IH
150
V
EE
V
IH
150
V
EE
V
IH
150
mV
V
th
Input Threshold Reference Voltage
Range (Note 20)
V
EE
+
950
V
CC
–75
V
EE
+
950
V
CC
–75
V
EE
+
950
V
CC
–75
mV
V
ISE
Single−Ended Input Voltage (V
IH
V
IL
)
150 2600 150 2600 150 260 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 5 & 7) (Note 21)
V
IHD
Differential Input HIGH Voltage V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
V
EE
+
1200
V
CC
mV
V
ILD
Differential Input LOW Voltage V
EE
V
CC
75
V
EE
V
CC
75
V
EE
V
CC
75
mV
V
ID
Differential Input Voltage
(V
IHD
– V
ILD
)
75 2600 75 2600 75 2600 mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Note 22) (Figure 8)
V
EE
+
1200
0 V
EE
+
1200
0 V
EE
+
1200
0 mV
I
IH
Input HIGH Current (@V
IH
) 80 150 80 150 80 150
mA
I
IL
Input LOW Current (@V
IL
) 25 100 25 100 25 100
mA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor 45 50 55 45 50 55 45 50 55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
CC
.
18.All loading with 50 W to V
CC
− 2 V.
19.Vth, V
IH
, V
IL,
and V
ISE
parameters must be complied with simultaneously.
20.Vth is applied to the complementary input when operating in single−ended mode. V
th
= (V
IH
− V
IL
) / 2.
21.V
IHD
, V
ILD,
V
ID
and V
IHCMR
parameters must be complied with simultaneously.
22.V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differen-
tial input signal.
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Table 8. AC CHARACTERISTICS V
CC
= 0 V; V
EE
= −3.465 V to −2.375 V or V
CC
= 2.375 V to 3.465 V; V
EE
= 0 V
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
f
max
Maximum Input Clock Frequency
(See Figure 3. F
max
/JITTER) (Note 23)
10.5 12 10.5 12 10.5 12 GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
90 125 160 90 125 160 90 125 160 ps
t
SKEW
Duty Cycle Skew (Note 24)
Within−Device Skew (Note 25)
Device−to−Device Skew (Note 26)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
ps
t
JITTER
RMS Random Clock Jitter
f
in
< 10 GHz
Peak−to−Peak Data Dependent Jitter
f
in
< 10 Gb/s
0.2
10.7
1 0.2
10.7
1 0.2
10.7
1
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 27)
75 2600 75 2600 75 2600 mV
t
r
t
f
Output Rise/Fall Times Q, Q
(20% − 80%) @ 1 GHz
15 30 55 20 30 55 20 30 55 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
23.Measured using a 500 mV source, 50% duty cycle clock source. All loading with 50 W to V
CC
− 2.0 V for QFN package. For minimum f
max
value of 10.5 GHz, output amplitude is approximately 200 mV (as shown in Figure 3, where output P−P spec is shown as a
minimum/guarantee of around 150 mV). Input edge rates 40 ps (20% − 80%).
24.See Figure 9. t
SKEW
= |t
PLH
− t
PHL
| for a nominal 50% Differential Clock Input Waveform.
25.Within−Device skew is defined as identical transitions on similar paths through a device.
26.Device−to−device skew for identical transitions at identical V
CC
levels.
27.V
INPP
(MAX) cannot exceed V
CC
− V
EE
.
0
100
200
300
400
500
600
123456789101112
INPUT FREQUENCY (GHz)
Figure 3. Output Amplitude (V
OUTPP
) vs. Input Frequency (F
IN
) at Ambient Temperature (Typical)
OUTPUT VOLTAGE AMPLITUDE (mV)
OUTPUT AMP.
OUTPUT P−P SPEC
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9
IN
V
th
IN
V
th
Figure 4. Differential Input Driven
Single−Ended
V
IH
V
IL
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
V
EE
V
th
IN
IN
V
ILDmax
V
IHDmax
V
IHDtyp
V
ILDtyp
V
IHDmin
V
ILDmin
V
IHCMR
V
EE
V
ID
= V
IHD
− V
ILD
V
CC
V
IHD
V
ILD
V
ID
= |V
IHD(IN)
− V
ILD(IN)|
IN
IN
Figure 5. Differential Inputs
Driven Differentially
Figure 6. V
th
Diagram Figure 7. Differential Inputs Driven Differentially
Figure 8. V
IHCMR
Diagram
IN
IN
V
IHCMRmax
V
IHCMRmin
IN

NBSG11MNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 2.5V/3.3V SiGE 1:2 Diff Clock w/RSECL
Lifecycle:
New from this manufacturer.
Delivery:
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