1. General description
The 74AHC125; 74AHCT125 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard JESD7-A.
The 74AHC125; 74AHCT125 provides four non-inverting buffer/line drivers with 3-state
outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH
at nOE causes the outputs to assume a high-impedance OFF-state.
The 74AHC125; 74AHCT125 is identical to the 74AHC126; 74AHCT126 but has active
LOW enable inputs.
2. Features
■ Balanced propagation delays
■ All inputs have a Schmitt-trigger action
■ Inputs accepts voltages higher than V
CC
■ For 74AHC125 only: operates with CMOS input levels
■ For 74AHCT125 only: operates with TTL input levels
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
◆ CDM JESD22-C101C exceeds 1000 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
74AHC125; 74AHCT125
Quad buffer/line driver; 3-state
Rev. 04 — 11 January 2008 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AHC125D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74AHCT125D
74AHC125PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74AHCT125PW
74AHC125BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
74AHCT125BQ
