LTC3851
13
3851fb
APPLICATIONS INFORMATION
V
IN
V
IN
INTV
CC
BOOST
TG
SW
BG
GND
INDUCTOR
DCRL
SENSE
+
SENSE
LTC3851
V
OUT
3851 F02
R1
R2
*PLACE C1 NEAR SENSE
+
, SENSE
PINS
C1*
R1||R2 • C1 =
R
SENSE(EQ)
= DCR
L
DCR
R2
R1 + R2
Figure 2. Current Mode Control Using the Inductor DCR
Slope Compensation and Inductor Peak Current
Slope compensation provides stability in constant
frequency architectures by preventing sub-harmonic
oscillations at high duty cycles. It is accomplished inter nally
by adding a compensating ramp to the inductor current
signal. Normally, this results in a reduction of maximum
inductor peak cur rent for duty cycles > 40%. However, the
LTC3851 uses a novel scheme that allows the maximum
inductor peak current to remain unaffected throughout
all duty cycles.
Inductor Value Calculation
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use of
smaller inductor and capacitor values. A higher frequency
generally results in lower effi ciency because of MOSFET
gate charge losses. In addition to this basic trade-off, the
effect of inductor value on ripple current and low current
operation must also be considered.
The inductor value has a direct effect on ripple current.
The inductor ripple current ∆I
L
decreases with higher
inductance or frequency and increases with higher V
IN
:
I
L
=
1
f•L
V
OUT
1–
V
OUT
V
IN
Accepting larger values of ∆I
L
allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆I
L
= 0.3(I
MAX
). The maximum
∆I
L
occurs at the maximum input voltage.
The inductor value also has secondary effects. The tran-
sition to Burst Mode operation begins when the average
inductor current required results in a peak current below
≈10% of the current limit determined by R
SENSE
. Lower
inductor values (higher ∆I
L
) will cause this to occur at
lower load currents, which can cause a dip in effi ciency in
the upper range of low current operation. In Burst Mode
operation, lower inductance values will cause the burst
frequency to increase.
Inductor Core Selection
Once the value for L is known, the type of inductor must
be selected. High effi ciency converters generally cannot
afford the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite or molypermalloy
cores. Actual core loss is independent of core size for a
xed inductor value, but it is very dependent on inductance
selected. As inductance increases, core losses go down.
Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode (Optional)
Selection
Two external power MOSFETs must be selected for the
LTC3851 controller: one N-channel MOSFET for the top
(main) switch, and one N-channel MOSFET for the bottom
(synchronous) switch.
LTC3851
14
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The peak-to-peak drive levels are set by the INTV
CC
voltage.
This voltage is typically 5V during start-up. Consequently,
logic-level threshold MOSFETs must be used in most ap-
plications. The only exception is if low input voltage is ex-
pected (V
IN
< 5V); then, sub-logic level threshold MOSFETs
(V
GS(TH)
< 3V) should be used. Pay close attention to the
BV
DSS
specifi cation for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the on-
resistance, R
DS(ON)
, Miller capacitance, C
MILLER
, input
voltage and maximum output current. Miller capacitance,
C
MILLER
, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C
MILLER
is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
at divided by the specifi ed change in V
DS
. This result is
then multiplied by the ratio of the application applied V
DS
to the gate charge curve specifi ed V
DS
. When the IC is
operating in continuous mode, the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle =
V
OUT
V
IN
Synchronous Switch Duty Cycle =
V
IN
–V
OUT
V
IN
The MOSFET power dissipations at maximum output
current are given by:
P
MAIN
=
V
OUT
V
IN
I
MAX
()
2
1
()
R
DS(ON)
+
V
IN
()
2
I
MAX
2
R
DR
()
C
MILLER
()
1
V
INTVCC
–V
TH(MIN)
+
1
V
TH(MIN)
(f)
P
SYNC
=
V
IN
–V
OUT
V
IN
I
MAX
()
2
1
()
R
DS(ON)
where δ is the temperature dependency of R
DS(ON)
and
R
DR
(approximately 2Ω) is the effective driver resistance
at the MOSFETs Miller threshold voltage. V
TH(MIN)
is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I
2
R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V
IN
< 20V,
the high current effi ciency generally improves with larger
MOSFETs, while for V
IN
> 20V, the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
MILLER
actually provides higher effi ciency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The optional Schottky diode conducts during the dead time
between the conduction of the two power MOSFETs. This
prevents the body diode of the bottom MOSFET from turn-
ing on, storing charge during the dead time and requiring
a reverse recovery period that could cost as much as 3%
in effi ciency at high V
IN
. A 1A to 3A Schottky is generally
a good size due to the relatively small average current.
Larger diodes result in additional transition losses due to
their larger junction capacitance.
Soft-Start and Tracking
The LTC3851 has the ability to either soft-start by itself
with a capacitor or track the output of another channel
or external supply. When the LTC3851 is confi gured to
soft-start by itself, a capacitor should be connected to
the TK/SS pin. The LTC3851 is in the shutdown state if
the RUN pin voltage is below 1.25V. TK/SS pin is actively
pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.25V, the LTC3851
powers up. A soft-start current of 1A then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
APPLICATIONS INFORMATION
LTC3851
15
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0V to 0.8V on the TK/SS pin. The total soft-start time can
be calculated as:
t
SOFT-START
= 0.8
C
SS
1.0µA
Regardless of the mode selected by the MODE/PLLIN pin,
the regulator will always start in pulse-skipping mode up
to TK/SS = 0.64V. Between TK/SS = 0.64V and 0.72V, it
will operate in forced continuous mode and revert to the
selected mode once TK/SS > 0.72V. The output ripple
is minimized during the 80mV forced continuous mode
window.
When the regulator is confi gured to track another supply,
the feedback voltage of the other supply is duplicated by a
resistor divider and applied to the TK/SS pin. Therefore, the
voltage ramp rate on this pin is determined by the ramp rate
of the other supplys voltage. Note that the small soft-start
capacitor charging current is always fl owing, producing
a small offset error. To minimize this error, one can select
the tracking resistive divider value to be small enough to
make this error negligible.
In order to track down another supply after the soft-start
phase expires, the LTC3851 must be confi gured for forced
continuous operation by connecting MODE/PLLIN to
INTV
CC
.
Output Voltage Tracking
The LTC3851 allows the user to program how its output
ramps up and down by means of the TK/SS pins. Through
this pin, the output can be set up to either coincidentally or
ratiometrically track with another supplys output, as shown
in Figure 3. In the following discussions, V
MASTER
refers to
a master supply and V
OUT
refers to the LTC3851’s output
as a slave supply. To implement the coincident tracking
in Figure 3a, connect a resistor divider to V
MASTER
and
connect its midpoint to the TK/SS pin of the LTC3851. The
ratio of this divider should be selected the same as that of
the LTC3851’s feedback divider as shown in Figure 4a. In
this tracking mode, V
MASTER
must be higher than V
OUT
.
To implement ratiometric tracking, the ratio of the resistor
divider connected to V
MASTER
is determined by:
V
OUT
V
MASTER
=
R2
R4
R3+R4
R1+R2
So which mode should be programmed? While either
mode in Figure 4 satisfi es most practical applications,
the coincident mode offers better output regulation.
This concept can be better understood with the help of
Figure 5. At the input stage of the error amplifi er, two
common anode diodes are used to clamp the equivalent
reference voltage and an additional diode is used to match
the shifted common mode voltage. The top two current
sources are of the same amplitude. In the coincident
APPLICATIONS INFORMATION
TIME
(3a) Coincident Tracking
V
MASTER
V
OUT
OUTPUT VOLTAGE
V
MASTE
R
V
OUT
TIME
3851 F03
(3b) Ratiometric Tracking
OUTPUT VOLTAGE
Figure 3. Two Different Modes of Output Voltage Tracking

LTC3851IGN#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Sync Buck Sw Reg Cntr
Lifecycle:
New from this manufacturer.
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