Philips Semiconductors Product specification
74F1668-bit bidirectional universal shift register
2
Feb. 14, 1991 853–0349 01718
FEATURES
• High impedance NPN base inputs for reduced loading
(20µA in high and low states)
• Synchronous parallel to serial applications
• Synchronous serial data input for easy expansion
• Clock enable for ”do nothing” mode
• Asynchronous master reset
• Expandable to 16 bits in 8–bit increments
• Industrial temperature range available (–40°C to +85°C)
DESCRIPTION
The 74F166 is a high speed 8–bit shift register that has fully
synchronous serial parallel data entry selected by an active
low parallel enable (PE
) input. When the PE is low one setup
time before the low–to–high clock transition, parallel data is
entered into the register.
When PE
is high, data is entered into internal bit position Q0
from serial data input (Ds), and the remaining bits are shifted
one place to the right (Q0 → Q1 → Q2, etc.) with each
positive going clock transition.
For expansion of the register in parallel to serial converters,
the Q7 output is connected to the Ds input of the succeeding
stage. The clock input is gated OR structure which allows
one input to be used as an active–low clock enable (CE
)
input. The pin assignment for the CP and CE
inputs is
arbitrary and can be reversed for layout convenience. The
low–to–high transition of CE
input should only take place
while the CP is high for predictable operation. A low on the
master reset (MR
) input overrides all other inputs and clears
the register asynchronously, forcing all bit positions to a low
state.
TYPE TYPICAL f
max
TYPICAL SUPPLY CUR-
RENT( TOTAL)
74F166 175MHz 50mA
ORDERING INFORMATION
ORDER CODE
COMMERCIAL RANGE INDUSTRIAL RANGE
DESCRIPTION
V
CC
= 5V ±10%, V
CC
= 5V ±10%,
PKG DWG #
T
amb
= 0°C to +70°C T
amb
= –40°C to +85°C
16–pin plastic DIP N74F166N I74F166N SOT38-4
16–pin plastic SO N74F166D I74F166D SOT109-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION 74F (U.L.) HIGH/
LOW
LOAD VALUE HIGH/
LOW
D0 – D7 Parallel data inputs 1.0/0.033
20µA/20µA
Ds Serial data input (shift right) 2.0/0.066
40µA/40µA
CP Clock input (active rising edge) 1.0/0.033
20µA/20µA
CE Clock enable input (active low) 1.0/0.033
20µA/20µA
PE Parallel enable input (active low) 1.0/0.033
20µA/20µA
MR Master reset input (active low) 2.0/0.066
40µA/40µA
Q7 Data output 50/33
1.0mA/20mA
Note to input and output loading and fan out table
1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.
