ADF4116/ADF4117/ADF4118
Rev. D | Page 13 of 28
PHASE FREQUENCY DETECTOR (PFD)
AND CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them.
Figure 28 is a simplified schematic of
the PFD. The PFD includes a fixed delay element that sets the
width of the antibacklash pulse. This is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
DELAY
U3
CLR1
Q1D1
CP
DOWN
UP
HI
U1
CLR2
Q2D2
U2
HI
N DIVIDER
R DIVIDER
P
CHARGE
PUMP
CPGND
R DIVIDER
CP OUTPUT
N DIVIDER
00392-028
Figure 28. PFD Simplified Schematic and Timing (In Lock)
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF411x family allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 in the function
latch.
Figure 33 shows the full truth table. Figure 29 shows the
MUXOUT section in block diagram form.
CONTROLMUX
DV
DD
MUXOUT
DGND
NALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
SDOUT
00392-029
Figure 29. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for both digital lock detect and
analog lock detect.
Digital lock detect is active high. It is set high when the phase
error on three consecutive phase detector cycles is less than
15 ns. It stays set high until a phase error greater than 25 ns is
detected on any subsequent PD cycle.
The N channel, open-drain, analog lock detect should be
operated with an external pull-up resistor of 10 kΩ nominal.
When lock is detected, it is high with narrow low going pulses.
INPUT SHIFT REGISTER
The ADF411x family digital section includes a 21-bit input shift
register, a 14-bit R counter, and an 18-bit N counter, comprising
a 5-bit A counter and a 13-bit B counter. Data is clocked into
the 21-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs, DB1 and DB0, as
shown in the timing diagram in
Figure 2. The truth table for
these bits is shown in
Figure 34. Table 5 summarizes how the
latches are programmed.
Table 5. Programming Data Latches
Control Bits
C2 C1 Data Latch
0 0 R Counter
0 1 N Counter (A and B)
1 0 Function Latch
1 1 Initialization Latch
