Rev B 4/28/15 2 LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER
83115I DATA SHEET
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 OE1 Input Pullup
Output enable pin. When LOW, forces outputs Q[2:7] to Hi-Z state.
5V tolerant. LVCMOS/LVTTL interface levels. See Table 3.
2, 3, 4, 7, 8,
11, 12, 13,
16, 17, 18,
21, 22, 25,
26, 27
Q0, Q1, Q2, Q3,
Q4, Q5, Q6,
Q7, Q8, Q9,
Q10, Q11, Q12,
Q13, Q14, Q15
Output
Single-ended clock outputs. 15
output impedance.
LVCMOS/LVTTL interface levels.
5, 6, 23, 24 V
DD
Power Positive supply pins.
9, 10, 19, 20 GND Power Power supply ground.
14 IN Input Pulldown Single-ended clock input. 5V tolerant. LVCMOS/LVTTL interface levels.
15 OE0 Input Pullup
Output enable pin. When LOW, forces outputs Q[8:13] to Hi-Z state.
5V tolerant. LVCMOS/LVTTL interface levels. See Table 3.
28 OE2 Input Pullup
Output enable pin. When LOW, forces outputs Q[0:1] and Q[14:15] to
Hi-Z state. 5V tolerant. LVCMOS/LVTTL interface levels.
See Table 3.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
C
PD
Power Dissipation Capacitance
(per output); NOTE 1
V
DD
= 3.465V 11 pF
R
OUT
Output Impedance V
DD
= 3.3V 15
