Rev B 4/28/15 4 LOW SKEW, 1-TO-16 LVCMOS/LVTTL FANOUT BUFFER
83115I DATA SHEET
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
DD
/2. See Parameter Measurement Information, Output Load Test Circuit diagram.
AC Electrical Characteristics
Table 5. AC Characteristics, V
DD
= 3.3V ± 5%, T
A
= -40°C to 85°C
All parameters measured at f
MAX
unless noted otherwise.
NOTE 1: Measured from V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
OE0:OE2 2 V
DD
+ 0.3 V
IN 2 V
DD
+ 0.3 V
V
IL
Input Low Voltage
OE0:OE2 -0.3 0.8 V
IN -0.3 1.3 V
I
IH
Input High Current
OE0:OE2 V
DD
= V
IN
= 3.465V 5 µA
IN V
DD
= V
IN
= 3.465V 150 µA
I
IL
Input Low Current
OE0:OE2 V
DD
= 3.465V, V
IN
= 0V -150 µA
IN V
DD
= 3.465V, V
IN
= 0V -5 µA
V
OH
Output High Voltage; NOTE 1 V
DD
= 3.3V ± 5% 2.6 V
V
OL
Output Low Voltage; NOTE 1 V
DD
= 3.3V ± 5% 0.5 V
I
OZL
Output Hi-Z Current Low 5µA
I
OZH
Output Hi-Z Current High 5µA
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 200 MHz
tjit(
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Integration Range: 12kHz – 20MHz 0.20 ps
tp
LH
Propagation Delay; NOTE 1 ƒ 200MHz 1.7 2.4 3.1 ns
tsk(o) Output Skew; NOTE 2, 4
Measured on the Rising Edge @
V
DD
/2
150 250 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4
Measured on the Rising Edge @
V
DD
/2
800 ps
t
R
/ t
F
Output Rise/Fall Time4 20% to 80% 400 800 ps
odc Output Duty Cycle 45 55 %
t
EN
Output Enable Time 20 ns
t
DIS
Output Disable Time 20 ns
