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CS5422GDR16

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CS5422
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13
Both logic level and standard FETs can be used.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail−to−rail due to overshoot caused by the
capacitive load they present to the controller IC.
Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component’s
junction temperature to exceed 150°C.
The maximum RMS current through the switch can be
determined by the following formula:
I
RMS(H) +
ƪ
I
L(PEAK)
2
) (I
L(PEAK)
I
L(VALLEY)
)
) I
L(VALLEY)
2
D
ƫ
3
Ǹ
where:
I
RMS(H)
= maximum switching MOSFET RMS current;
I
L(PEAK)
= inductor peak current;
I
L(VALLEY)
= inductor valley current;
D = duty cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
P
RMS(H)
+ I
RMS(H)
2
R
DS(ON)
where:
P
RMS(H)
= switching MOSFET conduction losses;
I
RMS(H)
= maximum switching MOSFET RMS current;
R
DS(ON)
= FET drain−to−source on−resistance
The upper MOSFET switching losses are caused during
MOSFET switch−on and switch−off and can be determined
by using the following formula:
P
SWH
+ P
SWH(ON)
) P
SWH(OFF)
+
V
IN
I
OUT
(t
RISE
) t
FALL
)
6T
where:
P
SWH(ON)
= upper MOSFET switch−on losses;
P
SWH(OFF)
= upper MOSFET switch−off losses;
V
IN
= input voltage;
I
OUT
= load current;
t
RISE
= MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
t
FALL
= MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/f
SW
= period.
The total power dissipation in the switching MOSFET can
then be calculated as:
P
HFET(TOTAL)
+ P
RMS(H)
) P
SWH(ON)
) P
SWH(OFF)
where:
P
HFET(TOTAL)
= total switching (upper) MOSFET losses;
P
RMS(H)
= upper MOSFET switch conduction Losses;
P
SWH(ON)
= upper MOSFET switch−on losses;
P
SWH(OFF)
= upper MOSFET switch−off losses;
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
T
J
+ T
A
) [P
HFET(TOTAL)
R
QJA
]
where:
T
J
= FET junction temperature;
T
A
= ambient temperature;
P
HFET(TOTAL)
= total switching (upper) FET losses;
R
ΘJA
= upper FET junction−to−ambient thermal resistance.
Selection of the Synchronous (Lower) FET
The switch conduction losses for the lower FET can be
calculated as follows:
+ [I
OUT
(1 * D)
Ǹ
]
2
R
DS(ON)
P
RMS(L)
+ I
RMS
2
R
DS(ON)
where:
P
RMS(L)
= lower MOSFET conduction losses;
I
OUT
= load current;
D = Duty Cycle;
R
DS(ON)
= lower FET drain−to−source on−resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
P
SWL
+ V
SD
I
LOAD
non−overlap time f
SW
where:
P
SWL
= lower FET switching losses;
V
SD
= lower FET source−to−drain voltage;
I
LOAD
= load current;
Non−overlap time = GATE(L)−to−GATE(H) or
GATE(H)−to−GATE(L) delay (from CS5422 data sheet
Electrical Characteristics section);
f
SW
= switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
P
LFET(TOTAL)
+ P
RMS(L)
) P
SWL
where:
P
LFET(TOTAL)
= Synchronous (lower) FET total losses;
P
RMS(L)
= Switch Conduction Losses;
P
SWL
= Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
T
J
+ T
A
) [P
LFET(TOTAL)
R
QJA
]
where:
T
J
= MOSFET junction temperature;
T
A
= ambient temperature;
P
LFET(TOTAL)
= total synchronous (lower) FET losses;
R
ΘJA
= lower FET junction−to−ambient thermal resistance.
CS5422
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14
Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, V
CC
, and the CS5422 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
) P
GATE(L)1
) P
GATE(H)2
) P
GATE(L)2
P
CONTROL(IC)
+ I
CC1
V
CC1
) I
BST
V
BST )
P
GATE(H)1
where:
P
CONTROL(IC)
= control IC power dissipation;
I
CC1
= IC quiescent supply current;
V
CC1
= IC supply voltage;
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
P
GATE(L)
= lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are:
P
GATE(H)
+ Q
GATE(H)
f
SW
V
BST
where:
P
GATE(H)
= upper MOSFET gate driver (IC) losses;
Q
GATE(H)
= total upper MOSFET gate charge at V
CC
;
f
SW
= switching frequency;
The lower (synchronous) MOSFET gate driver (IC)
losses are:
P
GATE(L)
+ Q
GATE(L)
f
SW
V
CC
where:
P
GATE(L)
= lower MOSFET gate driver (IC) losses;
Q
GATE(L)
= total lower MOSFET gate charge at V
CC
;
f
SW
= switching frequency;
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
Current Sensing
The current supplied to the load can be sensed easily using
the IS+ and IS− pins for the output. These pins sense a
voltage, proportional to the output current, and compare it to
a fixed internal voltage threshold. When the differential
voltage exceeds 70 mV, the internal overcurrrent protection
system goes into hiccup mode. Two methods for sensing the
current are available.
Sense Resistor. A sense resistor can be added in series
with the inductor. When the voltage drop across the sense
resistor exceeds the internal voltage threshold of 70 mV, a
fault condition is set.
The sense resistor is selected according to:
R
SENSE
+
0.070 V
I
LIMIT
In a high current supply, the sense resistor will be a very
low value, typically less than 10 mΩ. Such a resistor can be
either a discrete component or a PCB trace. The resistance
value of a discrete component can be more precise than a
PCB trace, but the cost is also greater.
Setting the current limit using an external sense resistor is
very precise because all the values can be designed to
specific tolerances. However, the disadvantage of using a
sense resistor is its additional constant power loss and heat
generation.
Inductor ESR. Another means of sensing current is to use
the intrinsic resistance of the inductor. A model of an
inductor reveals that the windings of an inductor have an
effective series resistance (ESR).
The voltage drop across the inductor ESR can be
measured with a simple parallel circuit: an RC integrator. If
the value of R
S1
and C are chosen such that:
L
ESR
+ R
S1
C
then the voltage measured across the capacitor C will be:
V
C
+ ESR I
LIM
Selecting Components.
Select the capacitor C first. A
value of 0.1 μF is recommended. The value of R
S1
can be
selected according to:
R
S1
+
1
ESR C
Typical values for inductor ESR range in the low m;
consult manufacturer’s datasheet for specific details.
Selection of components at these values will result in a
current limit of:
I
LIM
+
0.070 V
ESR
Figure 9. Inductor ESR Current Sensing
GATE(H)
V
CC
Co
GATE(L)
IS+
IS−
RS1
C
ESR
L
Given an ESR value of 3.5 mΩ, the current limit becomes
20 A. If an increased current limit is required, a resistor
divider can be added.
The advantages of setting the current limit by using the
winding resistance of the inductor are that efficiency is
maximized and heat generation is minimized. The tolerance
of the inductor ESR must be factored into the design of the
current limit. Finally, one or two more components are
required for this approach than with resistor sensing.
Adding External Slope Compensation
Today’s voltage regulators are expected to meet very
stringent load transient requirements. One of the key factors
in achieving tight dynamic voltage regulation is low ESR.
Low ESR at the regulator output results in low output
voltage ripple. The consequence is, however, that very little
voltage ramp exists at the control IC feedback pin (V
FB
),
resulting in increased regulator sensitivity to noise and the
potential for loop instability. In applications where the
CS5422
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15
internal slope compensation is insufficient, the performance
of the CS5422−based regulator can be improved through the
addition of a fixed amount of external slope compensation
at the output of the PWM Error Amplifier (the COMP pin)
during the regulator off−time. Referring to Figure 8, the
amount of voltage ramp at the COMP pin is dependent on the
gate voltage of the lower (synchronous) FET and the value
of resistor divider formed by R1and R2.
V
SLOPECOMP
+ V
GATE(L)
ǒ
R2
R1 ) R2
Ǔ
(1 * e
−t
t
)
where:
V
SLOPECOMP
= amount of slope added;
V
GATE(L)
= lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = t
ON
or t
OFF
(switch off−time);
τ = RC constant determined by C1 and the parallel
combination of R1, R2 neglecting the low driver
output impedance.
Figure 10. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
Each On−Time Cycle
To Synchronous
FET
C1
R2
R1
CS5422
GATE(L)
COMP
C
COMP
The artificial voltage ramp created by the slope
compensation scheme results in improved control loop
stability provided that the RC filter time constant is smaller
than the off−time cycle duration (time during which the
lower MOSFET is conducting). It is important that the series
combination of R1 and R2 is high enough in resistance to
avoid loading the GATE(L) pin. Also, C1 should be very
small (less than a few nF) to avoid heating the part.
EMI MANAGEMENT
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
LAYOUT GUIDELINES
When laying out the CPU buck regulator on a printed
circuit board, the following checklist should be used to
ensure proper operation of the CS5422.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
2. Keep high currents out of sensitive ground
connections.
3. Avoid ground loops as they pick up noise. Use star or
single point grounding.
4. For high power buck regulators on double−sided
PCB’s a single ground plane (usually the bottom) is
recommended.
5. Even though double sided PCB’s are usually
sufficient for a good layout, four−layer PCB’s are the
optimum approach to reducing susceptibility to
noise. Use the two internal layers as the power and
GND planes, the top layer for power connections and
component vias, and the bottom layers for the noise
sensitive traces.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous FETs
close together.
7. The MOSFET gate traces to the IC must be short,
straight, and wide as possible.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
9. Place the switching MOSFET as close to the input
capacitors as possible.
10. Place the output capacitors as close to the load as
possible.
11. Place the COMP capacitor as close as possible to the
COMP pin.
12. Connect the filter components of the following pins:
R
OSC,
V
FB
, V
OUT
, and COMP to the GND pin with a
single trace, and connect this local GND trace to the
output capacitor GND.
13. Place the V
CC
bypass capacitors as close as possible
to the IC.
14. Place the R
OSC
resistor as close as possible to the
R
OSC
pin.
15. Include provisions for 100−100pF capacitor across
each resistor of the feedback network to improve
noise immunity and add COMP.
16. Assign the output with lower duty cycle to channel 2,
which has better noise immunity.
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CS5422GDR16

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Description:
IC REG CTRLR BUCK 16SOIC
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