CS5422
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4
ELECTRICAL CHARACTERISTICS (0°C < T
A
< 70°C; 0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1 μF,
10.8 V < V
CC
< 13.2 V; 10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF, unless otherwise specified.)
Characteristic Test Conditions Min Typ Max Unit
Error Amplifier
V
FB1(2)
Bias Current V
FB1(2)
= 0 V 0.5 1.6 μA
V
FB1(2)
Input Range 0 1.1 V
COMP1,2 Source Current COMP1,2 = 1.2 V to 2.5 V; V
FB1(2)
= 0.8 V 15 30 60 μA
COMP1,2 Sink Current COMP1,2 = 1.2 V; V
FB1(2)
= 1.2 V 15 30 60 μA
Reference Voltage 1(2) COMP1 = V
FB1
; COMP2 = V
FB2
0.980 1.000 1.020 V
COMP1,2 Max Voltage V
FB1(2)
= 0.8 V 3.0 3.3 V
COMP1,2 Min Voltage V
FB1(2)
= 1.2 V 0.25 0.35 V
Open Loop Gain 95 dB
Unity Gain Band Width 40 kHz
PSRR @ 1.0 kHz 70 dB
Transconductance 32 mmho
Output Impedance 2.5 MΩ
GATE(H) and GATE(L)
High Voltage (AC) Measure: V
CC
GATE(L)1,2;
BST GATE(H)1,2; Note 2
0 0.5 V
Low Voltage (AC) Measure:GATE(L)1,2 or GATE(H)1,2; Note 2 0 0.5 V
Rise Time 1.0 V < GATE(L)1,2 < V
CC
1.0 V
1.0 V < GATE(H)1,2 < BST 1.0 V,
BST 14 V
20 50 ns
Fall Time V
CC
1.0 > GATE(L)1,2 > 1.0 V
BST 1.0 > GATE(H)1,2 > 1.0 V,
BST 14 V
15 50 ns
GATE(H) to GATE(L) Delay GATE(H)1,2 < 2.0 V, GATE(L)1,2 > 2.0 V
BST 14 V
20 40 70 ns
GATE(L) to GATE(H) Delay GATE(L)1,2 < 2.0 V, GATE(H)1,2 > 2.0 V;
BST 14 V
20 40 70 ns
GATE(H)1(2) and GATE(L)1(2)
pulldown.
Resistance to GND
Note 2
50 125 280 kΩ
PWM Comparator
Transient Response COMP1,2 = 1.0 V, V
FB1(2)
= 0 to 1.2 V 150 300 ns
PWM Comparator Offset V
FFB1(2)
= 0 V; Increase COMP1,2 until
GATE(H)1,2 starts switching
0.30 0.45 0.60 V
Artificial Ramp Duty cycle = 50%, Note 2 40 70 100 mV
Minimum Pulse Width Note 2 300 ns
Oscillator
Switching Frequency R
OSC
= 61.9 k; Measure GATE(H)1; Note 2 112 150 188 kHz
Switching Frequency R
OSC
= 30.9 k; Measure GATE(H)1 224 300 376 kHz
Switching Frequency R
OSC
= 15.1 k; Measure GATE(H)1; Note 2 450 600 750 kHz
R
OSC
Voltage R
OSC
= 30.9 k, Note 2 0.970 1.000 1.030 V
Phase Difference 180 °
2. Guaranteed by design, not 100% tested in production.
CS5422
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5
ELECTRICAL CHARACTERISTICS (continued) (0°C < T
A
< 70°C; 0°C < T
J
< 125°C; R
OSC
= 30.9 k, C
COMP1,2
= 0.1 μF,
10.8 V < V
CC
< 13.2 V; 10.8 V < BST < 20 V, C
GATE(H)1,2
= C
GATE(L)1,2
= 1.0 nF, unless otherwise specified.)
Characteristic UnitMaxTypMinTest Conditions
Supply Currents
V
CC
Current COMP1,2 = 0 V (No Switching) 13 17 mA
BST Current COMP1,2 = 0 V (No Switching) 3.5 6.0 mA
Undervoltage Lockout
Start Threshold GATE(H) Switching; COMP1,2 charging 7.8 8.6 9.4 V
Stop Threshold GATE(H) not switching; COMP1,2 discharging 7.0 7.8 8.6 V
Hysteresis StartStop 0.5 0.8 1.5 V
Hiccup Mode Overcurrent Protection
OVC Comparator Offset Voltage 0 V < IS+ 1(2) < 5.5 V, 0 V < IS 1(2) < 5.5 V 55 70 85 mV
Discharge Threshold 0.20 0.25 0.30 V
IS+ 1(2) Bias Current 0 V < IS+ 1(2) < 5.5 V 1.0 0.1 1.0 μA
IS 1(2) Bias Current 0 V < IS 1(2) < 5.5 V 1.0 0.1 1.0 μA
OVC Common Mode Range 0 5.5 V
OVC Latch COMP1 Discharge Current COMP1 = 1.0 V 2.0 5.0 8.0 μA
OVC Latch COMP2 Discharge Current COMP2 = 1.0 V 0.3 1.2 3.5 mA
COMP1 Charge/Discharge
Ratio in OVC
5.0 6.0 7.0
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6
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
PIN SYMBOL FUNCTION
SO16 SO24L
1 1 GATE(H)1 High Side Switch FET driver pin for channel 1.
2 2 GATE(L)1 Low Side Synchronous FET driver pin for channel 1.
3 GND Ground pin for all circuitry contained in the IC. This pin is internally
bonded to the substrate of the IC.
3 PGND Ground pin for the FET drivers.
4 4 BST Power input for GATE(H)1 and GATE(H)2 pins.
58, 1720 LGND Ground pin for the internal control circuitry. The pin is internally
bonded to the substrate of the IC.
5 9 IS+1 Positive input for channel 1 overcurrent comparator.
6 10 IS1 Negative input for channel 1 overcurrent comparator.
7 11 V
FB1
Error amplifier inverting input for channel 1.
8 12 COMP1 Channel 1 Error Amp output. PWM Comparator reference input. A
capacitor to LGND provides Error Amp compensation. The same
capacitor provides Soft Start timing for channel 1. This pin also
disables the channel 1 output when pulled below 0.3 V.
9 13 COMP2 Channel 2 Error Amp output. PWM Comparator reference input. A
capacitor to LGND provides Error Amp compensation and Soft
Start timing for channel 2. Channel 2 output is disabled when this
pin is pulled below 0.3 V.
10 14 V
FB2
Error amplifier inverting input for channel 2.
11 15 IS2 Negative input for channel 2 overcurrent comparator.
12 16 IS+2 Positive input for channel 2 overcurrent comparator.
13 21 R
OSC
Oscillator frequency pin. A resistor from this pin to ground sets the
oscillator frequency.
14 22 V
CC
Input Power supply pin.
15 23 GATE(L)2 Low Side Synchronous FET driver pin for channel 2.
16 24 GATE(H)2 High Side Switch FET driver pin for channel 2.

CS5422GDR16

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR BUCK 16SOIC
Lifecycle:
New from this manufacturer.
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