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CY7C15632KV18-450BZC

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CY7C15632KV18
72-Mbit QDR
®
II+ SRAM Four-Word
Burst Architecture (2.5 Cycle Read Latency)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-54932 Rev. *K Revised September 9, 2015
72-Mbit QDR
®
II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ Separate Independent Read and Write Data Ports
❐ Supports concurrent transactions
■ 500 MHz Clock for High Bandwidth
■ Four-word Burst for Reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1000 MHz) at 500 MHz
■ Available in 2.5 Clock Cycle Latency
■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■ Data Valid Pin (QVLD) to indicate Valid Data on the Output
■ Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
■ Separate Port selects for Depth Expansion
■ Synchronous Internally Self-timed Writes
■ QDR
®
II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to QDR I Device with one Cycle Read Latency
when DOFF
is asserted LOW
■ Available in × 18 Configuration
■ Full Data Coherency, providing Most Current Data
■ Core V
DD
= 1.8 V ± 0.1 V; I/O V
DDQ
= 1.4 V to V
DD
[1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL Inputs and Variable Drive HSTL Output Buffers
■ Available in 165-ball FBGA Package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible Test Access Port
■ Phase-Locked Loop (PLL) for Accurate Data Placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C15632KV18 – 4 M × 18
Functional Description
The CY7C15632KV18 is a 1.8 V Synchronous Pipelined SRAM,
equipped with QDR II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write addresses are latched on alternate rising edges of the
input (K) clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words that burst sequentially into or out of the device. Because
data is transferred into and out of the device on every rising edge
of both input clocks (K and K
), memory bandwidth is maximized
while simplifying system design by eliminating bus
“turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K
input clocks. All data outputs pass through output
registers controlled by the K or K
input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Description 500 MHz 450 MHz 400 MHz Unit
Maximum Operating Frequency 500 450 400 MHz
Maximum Operating Current × 18 850 780 710 mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
DDQ
= 1.4 V to V
DD
.
CY7C15632KV18
Document Number: 001-54932 Rev. *K Page 2 of 30
Logic Block Diagram – CY7C15632KV18
1M x 18 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
36
A
(19:0)
20
1M x 18 Array
1M x 18 Array
1M x 18 Array
18
CQ
CQ
DOFF
Q
[17:0]
QVLD
18
18
18
Write
Reg
Write
Reg
Write
Reg
18
CY7C15632KV18
Document Number: 001-54932 Rev. *K Page 3 of 30
Contents
Pin Configurations ...........................................................4
Pin Definitions ..................................................................5
Functional Overview ........................................................6
Read Operations .........................................................6
Write Operations .........................................................6
Byte Write Operations .................................................6
Concurrent Transactions .............................................7
Depth Expansion .........................................................7
Programmable Impedance ..........................................7
Echo Clocks ................................................................7
Valid Data Indicator (QVLD) ........................................7
PLL ..............................................................................7
Application Example ........................................................8
Truth Table ........................................................................9
Write Cycle Descriptions ...............................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................11
Disabling the JTAG Feature ......................................11
Test Access Port .......................................................11
Performing a TAP Reset ...........................................11
TAP Registers ...........................................................11
TAP Instruction Set ...................................................11
TAP Controller State Diagram .......................................13
TAP Controller Block Diagram ......................................14
TAP Electrical Characteristics ......................................14
TAP AC Switching Characteristics ...............................15
TAP Timing and Test Conditions ..................................16
Identification Register Definitions ................................17
Scan Register Sizes .......................................................17
Instruction Codes ...........................................................17
Boundary Scan Order ....................................................18
Power Up Sequence in QDR II+ SRAM .........................19
Power Up Sequence .................................................19
PLL Constraints .........................................................19
Maximum Ratings ...........................................................20
Operating Range .............................................................20
Neutron Soft Error Immunity .........................................20
Electrical Characteristics ...............................................20
DC Electrical Characteristics .....................................20
AC Electrical Characteristics .....................................21
Capacitance ....................................................................21
Thermal Resistance ........................................................21
AC Test Loads and Waveforms .....................................22
Switching Characteristics ..............................................23
Switching Waveforms ....................................................25
Read/Write/Deselect Sequence ................................25
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Package Diagram ............................................................27
Acronyms ........................................................................28
Document Conventions .................................................28
Units of Measure .......................................................28
Document History Page .................................................29
Sales, Solutions, and Legal Information ......................30
Worldwide Sales and Design Support ....................... 30
Products ....................................................................30
PSoC® Solutions ......................................................30
Cypress Developer Community .................................30
Technical Support .....................................................30
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CY7C15632KV18-450BZC

Mfr. #:
Buy CY7C15632KV18-450BZC
Manufacturer:
Cypress Semiconductor
Description:
SRAM 72MB (4Mx18) 1.8v 450MHz QDR II SRAM
Lifecycle:
New from this manufacturer.
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