Document Number: 001-54932 Rev. *K Page 6 of 30
Functional Overview
The CY7C15632KV18 is a synchronous pipelined Burst SRAM
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and flows out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR II+ completely
eliminates the need to “turnaround” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 18-bit data transfers in two clock
cycles.
These devices operate with a read latency of two and half cycles
when DOFF
pin is tied HIGH. When DOFF pin is set LOW or
connected to V
SS
then device behaves in QDR I mode with a
read latency of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K
).
All synchronous data inputs (D
[x:0]
) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q
[x:0]
) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K
) as well.
All synchronous control (RPS
, WPS, NWS
[x:0]
, BWS
[x:0]
) inputs
pass through input registers controlled by the rising edge of the
input clocks (K and K
).
CY7C15632KV18 is described in the following sections.
Read Operations
The CY7C15632KV18 is organized internally as four arrays of
1 M × 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS
active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K
clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q
[17:0]
using K as the output timing reference. On the
subsequent rising edge of K, the next 18-bit data word is driven
onto the Q
[17:0]
. This process continues until all four 18-bit data
words have been driven out onto Q
[17:0]
. The requested data is
valid 0.45 ns from the rising edge of the input clock (K or K
). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K
).
When the read port is deselected, the CY7C15632KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K
). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D
[17:0]
is latched and stored into
the lower 18-bit write data register, provided BWS
[1:0]
are both
asserted active. On the subsequent rising edge of the negative
input clock (K
) the information presented to D
[17:0]
is also stored
into the write data register, provided BWS
[1:0]
are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The
72 bits of data are then written into the memory array at the
specified location. Therefore, write accesses to the device can
not be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second write request. Write
accesses can be initiated on every other rising edge of the
positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K
).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C15632KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS
0
and
BWS
1
, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
V
REF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
V
DD
Power Supply Power Supply Inputs to the Core of the Device
V
SS
Ground Ground for the Device
V
DDQ
Power Supply Power Supply Inputs for the Outputs of the Device
Pin Definitions (continued)
Pin Name I/O Pin Description
