CY7C132, CY7C136
CY7C136A, CY7C142,
CY7C146
Document #: 38-06031 Rev. *H Page 7 of 17
Interrupt Timing
[16]
t
WINS
R/W to INTERRUPT Set Time 25 35 45 ns
t
EINS
CE to INTERRUPT Set Time 25 35 45 ns
t
INS
Address to INTERRUPT Set Time 25 35 45 ns
t
OINR
OE to INTERRUPT Reset Time
[13]
25 35 45 ns
t
EINR
CE to INTERRUPT Reset Time
[13]
25 35 45 ns
t
INR
Address to INTERRUPT Reset Time
[13]
25 35 45 ns
Switching Characteristics
Over the Operating Range (Speeds -35, -45, -55)
[8]
(continued)
Parameter Description
7C132-35
7C136-35
7C142-35
7C146-35
7C132-45
7C136-45
7C142-45
7C146-45
7C132-55
7C136-55
7C136A-55
7C142-55
7C146-55
Unit
Min Max Min Max Min Max
Switching Waveforms
Figure 4. Read Cycle No. 1 (Either Port-Address Access)
[17, 18]
Figure 5. Read Cycle No. 2 (Either Port-CE/OE )
[17, 19]
t
RC
t
AA
t
OHA
DATA VALIDPREVIOUS DATA VALID
DATA OUT
ADDRESS
t
ACE
t
LZOE
t
DOE
t
HZOE
t
HZCE
DATA VALID
DATA OUT
CE
OE
t
LZCE
t
PU
I
CC
I
SB
t
PD
Notes
17. R/W
is HIGH for read cycle.
18. Device is continuously selected, CE
= V
IL
and OE =
V
IL
.
19. Address valid prior to or coincident with CE
transition LOW.
CY7C132, CY7C136
CY7C136A, CY7C142,
CY7C146
Document #: 38-06031 Rev. *H Page 8 of 17
Figure 6. Read Cycle No. 3 (Read with BUSY Master: CY7C132 and CY7C136/CY7C136A)
Figure 7. Write Cycle No.1 (OE Three-States Data I/Os—Either Port)
[12, 20]
Switching Waveforms (continued)
t
BHA
t
BDD
VALID
t
DDD
t
WDD
ADDRESS MATCH
ADDRESS MATCH
R/W
R
ADDRESS
R
D
INR
ADDRESS
L
BUSY
L
DOUT
L
t
PS
t
BLA
t
RC
t
PWE
VALID
t
AW
t
WC
DATA VALID
HIGH IMPEDANCE
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HA
t
HZOE
CE
R/W
ADDRESS
OE
D
OUT
DATA
IN
Note
20. If OE
is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or t
HZWE
+ t
SD
to allow the data I/O pins to enter high impedance
and for data to be placed on the bus for the required t
SD
.
CY7C132, CY7C136
CY7C136A, CY7C142,
CY7C146
Document #: 38-06031 Rev. *H Page 9 of 17
Figure 8. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)
[12, 21]
Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)
Switching Waveforms (continued)
t
AW
t
WC
t
SCE
t
SA
t
PWE
t
HD
t
SD
t
HZWE
t
HA
HIGH IMPEDANCE
CE
R/W
ADDRESS
D
OUT
DATA
IN
t
LZWE
DATA VALID
ADDRESS MATCH
t
PS
CE
L
Valid First:
t
BLC
t
BHC
ADDRESS MATCH
t
PS
t
BLC
t
BHC
BUSY
L
CE
R
CE
L
ADDRESS
L,R
BUSY
R
CE
L
CE
R
ADDRESS
L,R
CE
R
Valid First:
Note
21. If the CE
LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state.

CY7C136-25JXCT

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 16K PARALLEL 52PLCC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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