NCN8024R
http://onsemi.com
10
bridge with R1 = 56 kW, R2 = 42 kW and V
POR−
= 1.20 V
typical the V
DD
dropout detection level can be increased up to:
UVLO +
59k ) 42k
42k
V
POR−
+ 2.75 V
The minimum dropout detection voltage should be higher
than 2 V.
The maximum detection level may be up to VDD.
CLOCK DIVIDER:
The input clock can be divided by 1/1, 1/2, 1/4, or 1/8,
depending upon the specific application, prior to be applied
to the smart card driver. These division ratios are
programmed using pins CLKDIV1 and CLKDIV2 (see
Table 1). The input clock is provided externally to pin
CLKIN.
Table 1. Clock Frequency Programming
CLKDIV1 CLKDIV2 F
CRD_CLK
0 0 CLKIN/8
0 1 CKLKIN / 4
1 0 CLKIN
1 1 CLKIN / 2
The clock input stage (CLKIN) can handle a 27 MHz
maximum frequency signal. Of course, the ratio must be
defined by the user to cope with Smart Card considered in
a given application
In order to avoid any duty cycle out of the 45% / 55%
range specification, the divider is synchronized by the last
flip flop, thus yielding a constant 50% duty cycle, whatever
be the divider ratio 1/2, 1/4 or 1/8. On the other hand, the
output signal Duty Cycle cannot be guaranteed 50% if the
division ratio is 1 and if the input Duty Cycle signal is not
within the 46 − 56% range at the CLKIN input.
When the signal applied to CLKIN is coming from the
external controller, the clock will be applied to the card
under the control of the microcontroller or similar device
after the activation sequence has been completed.
DATA I/O, AUX1 and AUX2 LEVEL SHIFTERS
The three bidirectional level shifters I/O, AUX1 and
AUX2 adapt the voltage difference that might exist between
the micro−controller and the smart card. These three
channels are identical. The first side of the bidirectional
level shifter dropping Low (falling edge) becomes the driver
side until the level shifter enters again in the idle state pulling
High CRD_IO and I/Ouc.
Passive 11 kW pull−up resistors have been internally
integrated on each terminal of the bidirectional channel. In
addition with these pull−up resistors, an active pull−up
circuit provides a fast charge of the stray capacitance.
The current to and from the card I/O lines is limited
internally to 15 mA and the maximum frequency on these
lines is 1 MHz.
STANDBY MODE
After a Power−on reset, the circuit enters the standby
mode. A minimum number of circuits are active while
waiting for the microcontroller to start a session:
• All card contacts are inactive
• Pins I/Ouc, AUX1uc and AUX2uc are in the
high−impedance state (11 kW pull−up resistor to V
DD
)
• Card pins are inactive and pulled Low
• Supply Voltage monitoring is active
POWER−UP
In the standby mode the microcontroller can check the
presence of a card using the signals INT and CMDVCC as
shown in Table 2:
Table 2. Card Presence State
INT CMDVCC State
HIGH HIGH Card present
LOW HIGH Card not present
If a card is detected present (CRD_PRES or CRD_PRES
active) the controller can start a card session by pulling
CMDVCC Low. Card activation is run (t0, Figure 5). This
Power−Up Sequence makes sure all the card related signals
are LOW during the CRD_V
CC
positive going slope. These
lines are validated when CRD_V
CC
is stable and above the
minimum voltage specified. When the CRD_V
CC
voltage
reaches the programmed value (3.0 V or 5.0 V), the circuit
activates the card signals according to the following
sequence (Figure 5):
• CRD_V
CC
is powered−up at its nominal value (t1)
• I/O, AUX1 and AUX2 lines are activated (t2)
• Then Clock channel is activated and the clock signal is
applied to the card (typically 500 ns after I/Os lines)
(t3)
• Finally the Reset level shifter is enabled (typically
500 ns after clock channel) (t4)
The clock can also be applied to the card using a RSTIN
mode allowing controlling the clock starting by setting
RSTIN Low (Figure 4). Before running the activation
sequence, that is before setting Low CMDVCC RSTIN is set
High. The following sequence is applied:
• The Smart Card Interface is enable by setting
CMDVCC LOW (RSTIN is High).
• Between t2 (Figure 4) and t5 = 200 ms, RSTIN is reset
to LOW and CCLK will start precisely at this moment
allowing a precise count of clock cycles before toggling
CRST Low to High for ATR (Answer To Reset)
request.
• CRST remains LOW until 200 ms; after t5 = 200 ms
CRST is enabled and is the copy of RSTIN which has
no more control on the clock.
