NCN8024R
http://onsemi.com
9
SMART CARD INTERFACE SECTION, CRD_IO, CRD_AUX1, CRD_AUX2, CRD_CLK, CRD_RST, CRD_PRES,
CRD_PRES
(V
DD
= 3.3 V; V
DDP
= 5 V; T
amb
= 25°C; F
CLKIN
= 10 MHz)
Symbol UnitMaxTypMinRating
|I
IH
|
|I
IL
|
CRD_PRES, CRD_PRES
High level input leakage current, V
IH
= V
DD
CRD_PRES
CRD_PRES
Low level input leakage current, V
IL
= 0 V
CRD_PRES
CRD_PRES
3
3
10
1
1
10
mA
T
debounce
Debounce Time CRD_PRES and CRD_PRES (Note 7) 5 8 12 ms
I
CRD_IO
CRD_IO, CRD_AUX1, CRD_AUX2 Current Limitation − − 15 mA
I
CRD_CLK
CRD_CLK Current Limitation − − 70 mA
I
CRD_RST
CRD_RST Current Limitation − − 20 mA
t
act
Activation Time (Note 7) 30 − 100
ms
t
deact
Deactivation Time (Note 7) 30 − 250
ms
Temp
SD
Shutdown Temperature − 160 − °C
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed
circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the
declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device
specification limit values are applied individually under normal operating conditions and not valid simultaneously.
7. Guaranteed by design and characterization
POWER SUPPLY
The NCN8024R smart card interface has two power
supplies: V
DD
and V
DDP
.
V
DD
is usually common to the system controller and the
interface. The applied V
DD
ranges from 2.7 V up to 5.5 V.
If V
DD
goes below 2.30 V typical (UVLO
VDD
) a
power−down sequence is automatically performed. In that
case the interrupt (INT) pin is set Low.
A Low Drop−Out (LDO) and low noise regulator is used
to provide the 3 V or 5 V power supply voltage (CRD_V
CC
)
to the card. VDDP is the LDO’s input voltage. CRD_V
CC
is
the LDO output. The typical distributed reservoir output
capacitor connected to CRD_V
CC
is 100 nF + 220 nF. To
minimize dI/dt effects the capacitor of 100 nF is connected
as close as possible to the CRD_V
CC
’s pin and the 220 nF
one as close as possible to the card connector C1 pin. Both
feature very low ESR values (lower than 50 mW). The
decoupling capacitors on V
DD
and V
DDP
respectively
100 nF and 10 mF have also to be connected close to the
respective IC pins.
The CRD_VCC pin can source up to 70 mA continuously
over the VDDP range, the absolute maximum current being
internally limited below 150 mA (Typical at 120 mA).
There’s no specific sequence for applying V
DD
or V
DDP
.
They can be applied to the interface in any sequence. After
powering the device INT pin remains Low until a card is
inserted.
SUPPLY VOLTAGE MONITORING
The supply voltage monitoring block includes the Power
On Reset (POR) circuitry and the under voltage lockout
(UVLO) detection (V
DD
voltage dropout detection).
PORADJ pin allows the user, according to the considered
application, to adjust the V
DD
UVLO threshold. If not used
PORADJ pin is connected to Ground (recommended even
if it may be left unconnected).
The input supply voltage is continuously monitored to
prevent under voltage operation. At power up, the system
initializes the internal logic during POR timing and no
further signal can be provided or supported during this
period.
The system is ready to operate when the input voltage has
reached the minimum V
DD
. Considering this, the
NCN8024R will detect an Under−Voltage situation when
the input supply voltage will drop below 2.30 V typical.
When V
DD
goes down below the UVLO falling threshold a
deactivation sequence is performed.
The device is inactive during power−on and power−off of
the V
DD
supply (8 ms reset pulse).
PORADJ pin is used to modify the UVLO threshold
according to the below relationship considering an external
resistor divider R1 / R2 (see block diagram Figure 1):
UVLO +
R1 ) R2
R2
V
POR
If PORADJ is connected to Ground the V
DD
UVLO
threshold (V
DD
falling) is typically 2.30 V. In some cases it
can be interesting to adjust this threshold at a higher value
and by the way increase the V
DD
supply dropout detection
level which enables a deactivation sequence if the V
DD
voltage is too low.
For example, there are microcontrollers for which the
minimum supply voltage insuring a correct operating is
higher than 2.70 V, increasing UVLO
VDD
(V
DD
falling) is
consequently necessary. Considering for instance a resistor
