Data Sheet AD7490-EP
Rev. A | Page 7 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD7490-EP
T
OP
VIEW
(Not to Scale)
V
IN
11
1
V
IN
12
28
V
IN
10
2
V
IN
13
27
V
IN
9
3
V
IN
14
26
NC
4
V
IN
15
25
V
IN
8
5
AGND
24
V
IN
7
6
REF
IN
23
V
IN
6
7
V
DD
22
V
IN
5
8
AGND
21
V
IN
4
9
CS
20
V
IN
3
10
DIN
19
V
IN
2
11
NC
18
V
IN
1
12
V
DRIVE
17
V
IN
0
13
SCLK
16
AGND
14
DOUT
15
NC = NO CONNECT
AL
L NC PINS SHOULD BE
CONNECTED STRAIGHT TO AGND
08936-003
Figure 3. 28-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
20
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7490-EP and also frames the serial data transfer.
23 REF
IN
Reference Input for the AD7490-EP. An external reference must be applied to this input. The voltage range for the
external reference is 2.5 V ± 1% for specified performance.
22 V
DD
Power Supply Input. The V
DD
range for the AD7490-EP is from 2.7 V to 5.25 V. For the 0 V to 2 × REF
IN
range, V
DD
should be from 4.75 V to 5.25 V.
14, 21,
24
AGND Analog Ground. Ground reference point for all circuitry on the AD7490-EP. All analog/digital input signals and any
external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.
13 to 5,
3 to 1,
28 to 25
V
IN
0 to
V
IN
15
Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed into
the on chip track-and-hold. The analog input channel to be converted is selected by using the address bits ADD3
through ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the
sequence register to be programmed. The input range for all input channels can extend from 0 V to REF
IN
or 0 V to
2 × REF
IN
as selected via the RANGE bit in the control register. Any unused input channels should be connected to
AGND to avoid noise pickup.
19 DIN Data In. Logic input. Data to be written to the control register of the AD7490-EP is provided on this input and is
clocked into the register on the falling edge of SCLK (see the AD7490 data sheet).
15 DOUT Data Out. Logic output. The conversion result from the AD7490-EP is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four address bits
indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is
provided by MSB first. The output coding can be selected as straight binary or twos complement via the CODING
bit in the control register.
16 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the conversion process of the AD7490-E P.
17 V
DRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the
AD7490-EP operates.
