15
FN9107.3
June 30, 2005
perfect choice for these two supplies, as it is a dual regulator
and has independent PGOOD functions for each supply.
Once these two supplies are within regulation, PGOOD
Vccp
and PGOOD
Vcc_mch
will be high impedance, and will allow
the PGOOD of the ISL6217A to sink approximately 2.6mA to
ground through the internal MOSFET, shown in Figure 10.
The ISL6217A detects this current and starts an internal
PGOOD timer.
The current sourced into the PGOOD pin is critical for proper
start-up operation. The pullup resistor, R
pullup
is sized to
give approximately 2.6mA of current sourced into the
PGOOD pin when the system is enabled and the Vccp and
Vcc_mch supplies are in regulation.
As given in the electrical specifications of this document, the
PGOOD MOSFET r
DS(ON)
is given as 82Ω maximum. If
3.3V is used as the supply, then the pullup resistor is given
by the following equation:
where Vsource is the supply minus 5% for tolerance. This
will insure that approximately 2.6mA will be sourced into the
PGOOD pin for worst case conditions of low supply and
largest MOSFET r
DS(ON)
.
Once the proper level of PGOOD current is detected, the
ISL6217A then captures the VID and regulates to this value.
The PGOOD timer is a function of the internal clock and
switching frequency. The internal PGOOD delay can be
calculated as follows:
The ISL6217A controller regulates the CORE output voltage
to the VID command, and once the timer has expired, the
PGOOD output is allowed to go high.
NOTE: the PGOOD functions of the V
CC_CORE
, Vccp and
Vcc_mch regulators are wire OR’d together to create the system
signal “IMVP4_PWRGD”. If any of the supplies fall outside the
regulation window, their respective PGOOD pins are pulled low,
which forces IMVP4_PWRGD low. PGOOD of the ISL6217A is
internally disabled during all VID and Mode transitions.
Overvoltage
The VSEN voltage is compared with an internal overvoltage
protection (OVP) reference, set to 112% of the VID voltage.
If the VSEN voltage exceeds the OVP reference, a
comparator simultaneously sets the OV latch, and pulls the
PWM signal low. The drivers turn on the lower MOSFETs,
shunting the converter output to ground. Once the output
voltage falls below 102% of the set point, the high side and
low side MOSFETs are held off. This prevents dumping of
the output capacitors back through the output inductors and
lower MOSFETs, which would cause a negative voltage on
the CORE output.
This architecture eliminates the need of a high current,
Schottky diode on the output. If the overvoltage condition
persists, the outputs are cycled between output low and
output “off”, similar to a hysteretic regulator. The OV latch is
reset by cycling the VDD supply voltage to initiate a POR.
Depending on the mode of operation, the overvoltage set
point is 112% of the VID, Deep or Deeper Sleep set point.
Undervoltage
The VSEN pin is also compared to an undervoltage (UV)
reference which is set to 84% of the VID, Deep or Deeper
Sleep set point, depending on the mode of operation. If the
VSEN voltage is below the UV reference for more than 32
consecutive phase clock cycles, the power good monitor
triggers the PGOOD pin to go low, and latches the chip off
until power is reset to the chip, or the EN pin is toggled.
Overcurrent
The RISEN resistor scales the voltage sampled across the
lower MOSFET and provides current feedback proportional
to the output current of each active channel. Refer to
Figure 9. The ISEN currents from all the active channels are
averaged together to form a scaled version of the total
output current, I
AVERAGE
. I
AVERAGE
is compared with an
internally generated overcurrent trip threshold, which is
proportional to the current sourced from the OCSET pin,
I
OCSET
. The overcurrent trip current source is
programmable and described in the “Overcurrent Setting -
OCSET” section of this document.
If I
AVERAGE
exceeds the I
OCSET
level, an up/down
counter is enabled. If I
AVERAGE
does not fall below
I
OCSET
within 32 phase cycle counts, the PGOOD pin
transitions low and latches the chip off. If normal operation
resumes within the 32 phase cycle count window, the
controller will continue to operate normally. Refer to the
“Block Diagram”.
NOTE: due to “DROOP” there is inherent current limit, since load
current cannot exceed the amount that would command an output
voltage lower than 84% of the VID voltage. This would result in an
undervoltage shutdown, and would also cause the PGOOD pin to
transition low and latch the chip off.
Control Loops
The “Block Diagram” and Figure 9 shows a simplified
diagram of the voltage regulation and current control loops
for a two-phase converter. Both voltage and current
feedback are used to precisely regulate voltage and tightly
control output currents, I
L1
and I
L2
, of the two power
channels. The voltage loop is comprised of the Error
Amplifier, Comparators, Internal Gate Drivers, and
MOSFETs. The Error Amplifier drives the modulator to force
the FB pin to the IMVP-IV™ and IMVP-IV+™ reference
minus “Droop”.
()
()
Ω≈−
−
=−= k2.182
mA6.2
3.305.03.3
maxr
mA6.2
Vsource
R
DSONPullup
(EQ. 4)
Timer Delay = 3072 / FSW
(EQ. 5)
ISL6217A
