ISL6217ACVZ Datasheet ISL6217ACVZ, ISL6217ACVZ-T, ISL6217ACVZA-T | P16-P18

FN9107.3

June 30, 2005

Voltage Loop

The output CORE voltage feedback is applied to the Error

Amplifier through the compensation network. The signal

seen on the FB pin will drive the Error Amplifier output either

high or low, depending on the CORE voltage. A CORE

voltage level that is lower than the IMVP-IV™ and

IMVP-IV+™ reference, as output from the 6 bit DAC, makes

the amplifier output move towards a higher output voltage

level. The amplifier output voltage is applied to the positive

inputs of the comparators by the BALANCE summing

networks. Out-of-phase sawtooth signals are applied to the

two comparator inverting inputs. Increasing Error Amplifier

voltage results in increased Comparator output duty cycle.

This increased duty cycle signal is passed through the PWM

circuit to the internal gate-drive circuitry. The output of the

internal gate-drive is directly connected to the gate of the

MOSFETs. Increased duty cycle or ON-time for the high side

MOSFET transistors results in increased output voltage,

VCORE, to compensate for the low output voltage sensed.

Current Loop

The current control loop keeps the channel currents in

balance. During the PWM off-time of each channel, the

voltage Vr

DS(ON)

, developed across the lower MOSFET is

sampled. Internally, the ISEN pin is held at virtual ground

during this interval, and Vr

DS(ON)

is impressed across the

ISEN

resistor. This provides current feedback proportional

to the output current of each channel. The scaled output

currents from all active channels are combined to create an

average current reference I

AVERAGE

, proportional to the

converter total output current. This signal is then subtracted

from the individual channel scaled output currents to

produce a current correction signal for each channel. The

current correction signal keeps each channel output current

contribution balanced relative to the other active channels.

Each current correction signal is subtracted from the error

amplifier output and fed to the individual channel PWM

circuits. For example, assume the voltage sampled across

Q4 in Figure 9 is higher than that sampled across Q2. The

ISEN2 current would be higher than ISEN1. When the two

reference currents are averaged, they accurately represent

the total output current of the converter. The reference

current I

AVERAGE

is then subtracted from the ISEN

currents. This results in a positive offset for Channel 2 and a

negative offset for Channel 1. These offsets are subtracted

from the error amplifier signal and perform phase balance

correction. The V

ERROR2

signal is reduced, while

ERROR1

would be increased. The PWM circuit would then

reduce the pulse width to lower the output current

contribution by Channel 2, while doing the opposite to

Channel 1, thereby balancing channel currents.

Droop Compensation

Microprocessors and other peripherals tend to change their

load current demands from near no-load to full load often

during operation. These same devices require minimal

output voltage deviation during a load step.

A high di/dt load step will cause an output voltage spike. The

amplitude of the spike is dictated by the output capacitor

ESR, multiplied by the load step magnitude, plus the output

capacitor ESL, times the load step di/dt. A positive load step

produces a negative output voltage spike and vice versa. A

large number of low-series-impedance capacitors are often

used to prevent the output voltage deviation from exceeding

the tolerance of some devices. One widely accepted solution

to this problem is output voltage “Droop”, or active voltage

positioning.

As shown in Figure 3 and Figure 9, the average channel

current is used to control the “Droop” current source,

DROOP

. The “Droop” current source is a controlled current

source and is proportional to output current. This current

source is approximately 87% of the averaged ISEN currents.

The Droop current is sourced out of the SOFT pin through

the Droop resistor and returns through the EA+ pin. This

creates a “Droop” voltage V

DROOP

, which subtracts from

the IMVP- IV™ and IMVP-IV+™ reference voltage on SOFT

to generate the voltage set point for the CORE regulator.

Full load current for the Intel IMVP-IV™ and IMVP-IV+™

specification is 32A. Knowing that the Droop Current,

sourced out of the SOFT pin, will be 87% of the ISEN

averaged currents, a “Droop” resistor R

DROOP

, can be

selected to provide the amount of voltage “Droop” required

at full load. The selection of this resistor is explained in the

following section.

Selection of RDROOP

Figure 11 shows a static “Droop” load line for the 1.484V

Active Mode. The ISL6217A, as previously mentioned,

allows the programming of the load line slope by the

selection of the RDROOP resistor.

As per the Intel IMVP-IV™ and IMVP-IV+™ specification,

Droop = 0.003 (Ω). Therefore, 25A of full load current

equates to a 0.075V Droop output voltage from the VID

setpoint. Refer to Figure 3 and Figure 9, R

DROOP

can be

OUT,HI

OUT,LO

OUT,MAX

OUT,NL

OUT,NOM

OUT,MID

-3 m

load line

(25A,1.409V

)

(0A,1.506V)

(0A,1.484V)

(25A,1.431V

)

(0A,1.462V)

(25A,1.387V

)

STATIC TOLERANCE BANDS

NOMINAL "DROOP" LOAD LINE

FIGURE 11. IMVP-IV ACTIVE MODE STATIC LOAD LINE

ISL6217A

FN9107.3

June 30, 2005

selected based on R

ISEN

which is calculated through

Equation 3, r

DS(ON)

, and Droop as per the Block Diagram or

the following equation:

Diode Emulation

Diode emulation allows for higher converter efficiency under

light-load situations. With diode emulation active, the

ISL6217A will detect the zero current crossing of the output

inductor and turn off LGATE. This ensures that

discontinuous conduction mode (DCM) is achieved. In DCM,

conduction losses are reduced in the Low-Side MOSFET,

consequently boosting efficiency. The ISL6217A operates in

DCM in both deep and deeper sleep mode.

Adaptive Shoot-Through Protection

Both drivers incorporate adaptive shoot-through protection

to prevent upper and lower MOSFETs from conducting

simultaneously and shorting the input supply. This is

accomplished by ensuring the falling gate has turned off one

MOSFET before the other is allowed to turn on.

During turn-off of the lower MOSFET, the LGATE voltage is

monitored until it reaches a 1V threshold, at which time the

UGATE is released to rise. Adaptive shoot-through circuitry

monitors the upper MOSFET gate-to-source voltage during

UGATE turn-off. Once the upper MOSFET gate-to-source

voltage has dropped below a threshold of 1V, the LGATE is

allowed to rise.

Component Selection Guidelines

OUTPUT CAPACITOR SELECTION

Output capacitors are required to filter the output inductor

current ripple and supply the transient load current. The

filtering requirements are a function of the channel switching

frequency and the output ripple current. The load transient

requirements are a function of the slew rate (di/dt) and the

magnitude of the transient load current.

The microprocessor used for IMVP-IV™ and IMVP-IV+™

will produce transient load rates as high as 30A/ns. High

frequency, ceramic capacitors are used to supply the initial

transient current and slow the rate-of-change seen by the

bulk capacitors. Bulk filter capacitor values are generally

determined by the ESR (Effective Series Resistance) and

voltage rating requirements rather than actual capacitance

requirements. To meet the stringent requirements of

IMVP-IV™ and IMVP-IV+™, (15) 2.2µF, 0612 “Flip Chip”

high frequency, ceramic capacitors are placed very close the

Processor power pins, with care being taken not to add

inductance in the circuit board traces that could cancel the

usefulness of these low inductance components.

Specialized low-ESR capacitors, intended for switching

regulator applications, are recommended for the bulk

capacitors. The bulk capacitor ESR and ESL determine the

output ripple voltage and the initial voltage drop following a

high slew-rate transient edge. Recommended are at least (4)

4V, 220µF Sanyo Sp-Cap capacitors in parallel, or (5) 330µF

SP-Cap style capacitors. These capacitors provide an

equivalent ESR of less than 3mΩ. These components

should be laid out very close to the load.

As the sense trace for VSEN may be long and routed close

to switching nodes, a 1.0µF ceramic decoupling capacitor is

located between VSEN and ground at the ISL6217A.

Output Inductor Selection

The output inductor is selected to meet the voltage ripple

requirements and minimize the converter response time to a

load transient. In a multi-phase converter topology, the ripple

current of one active channel partially cancels with the other

active channels to reduce the overall ripple current. The

reduction in total output ripple current results in a lower

overall output voltage ripple.

The inductor selected for the power channels determines the

channel ripple current. Increasing the value of inductance

reduces the total output ripple current and total output

voltage ripple; however, increasing the inductance value will

slow the converter response time to a load transient.

One of the parameters limiting the converter response time

to a load transient is the time required to slew the inductor

current from its initial current level to the transient current

level. During this interval, the difference between the two

levels must be supplied by the output capacitance.

Minimizing the response time can minimize the output

capacitance required.

The channel ripple can be reasonably approximated by the

following equation:

The total output ripple current can be approximated from the

curves in Figure 10.

They provide the total ripple current as a function of duty

cycle and number of active channels, normalized to the

parameter K

NORM

at zero duty cycle,

Where L is the channel inductor value.

()

)(

Droop3.2R

)DSON(

ISEN

DROOP

Ω⋅⋅=

(EQ. 6)

OUT

OUTIN

I •

•

−

=∆

(EQ. 7)

OUT

NORM

•

(EQ. 8)

ISL6217A

FN9107.3

June 30, 2005

FIGURE 12. OUTPUT RIPPLE CURRENT MULTIPLIER vs

DUTY CYCLE

Find the intersection of the active channel curve and duty

cycle for your particular application. The resulting ripple

current multiplier from the y-axis is then multiplied by the

normalization factor K

NORM

, to determine the total output

ripple current for the given application. Find the intersection

of the active channel curve and duty cycle for your particular

application. The resulting ripple current multiplier from the y-

axis is then multiplied by the normalization factor K

NORM

, to

determine the total output ripple current for the given

application.

Input Capacitor Selection

Use a mix of input bypass capacitors to control the voltage

overshoot across the MOSFETs. Use ceramic capacitors for

the high frequency decoupling, and bulk capacitors to supply

the RMS current. Small ceramic capacitors must be placed

very close to the upper MOSFET to suppress the voltage

induced in the parasitic circuit impedances.

Two important parameters to consider when selecting the

bulk input capacitor are the voltage rating and the RMS

current rating. For reliable operation, select a bulk capacitor

with voltage, and current ratings above the maximum input

voltage and the largest RMS current required by the circuit.

The capacitor voltage rating should be at least 1.25 times

greater than the maximum input voltage and a voltage rating

of 1.5 times is a conservative guideline. The RMS current

requirement for a converter design can be approximated

with the aid of Figure 13.

Follow the curve for the number of active channels in the

converter design. Next determine the worst case duty cycle

for the converter and find the intersection of this value and

the active channel curve. The worst case duty cycle is

defined as the maximum operating CORE output voltage

divided by the minimum operating battery voltage. Find the

corresponding y-axis value, which is the current multiplier.

Multiply the total full load output current, not the channel

value, by the current multiplier value found, and the result is

the RMS input current which must be supported by the input

capacitors.

FIGURE 13. INPUT RMS RIPPLE CURRENT MULTIPLIER

MOSFET Selection and Considerations

For the Intel IMVP-IV™ and IMVP-IV+™ application, which

requires up to 25A of current, it is suggested that 2 channel

operation with (3) MOSFETs per channel be implemented.

This configuration would be: (1) High Switching Frequency,

Low Gate Charge MOSFET for the Upper, and (2) Low

DS(ON)

MOSFETs for the Lowers.

In high-current PWM applications, the MOSFET power

dissipation, package selection and heatsink are the

dominant design factors. The power dissipation includes two

loss components: conduction loss and switching loss. These

losses are distributed between the upper and lower

MOSFETs according to duty cycle of the converter. Refer to

the PUPPER and PLOWER equations below. The

conduction losses are the main component of power

dissipation for the lower MOSFETs. Only the upper

MOSFETs have significant switching losses, since the lower

devices turn on and off into near zero voltage. The following

equations assume linear voltage-current transitions and do

not model power loss due to the reverse-recovery of the

lower MOSFETs body diode. The gate-charge losses are

dissipated in the ISL6217A drivers and do not heat the

MOSFETs; however, large gate-charge increases the

switching time t

SW,

which increases the upper MOSFET

switching losses. Ensure that both MOSFETs are within their

maximum junction temperature, at high ambient

temperature, by calculating the temperature rise according

to package thermal-resistance specifications.

CMNORMTOTAL

KKI •=∆

(EQ. 9)

()

OUTINONDS

LOWER

VVrI

−××

(EQ. 10)

ISL6217A

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

ISL6217ACVZ

Mfr. #:

Buy ISL6217ACVZ

Manufacturer:

Renesas / Intersil

Description:

Switching Controllers P6 PWM CNTRLR FOR IMVP4 W/DIODE EMULAT

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ISL6217ACVZ

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