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MAX5953DUTM+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
MAX5953A/MAX5953B/MAX5953C/MAX5953D
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (DC-DC Controller)
(All voltages referenced to GND, unless otherwise noted. V
HVIN
= +48V, C
INBIAS
= 1µF, C
REGOUT
= 2.2µF, R
RTCT
= 25kΩ, C
RTCT
=
100pF, C
BST
= 0.22µF, V
CSS
= V
CS
= 0V, V
RAMP
= V
DCUVLO
= 3V, T
J
= 0°C to +125°C, unless otherwise noted. Typical values are at
T
J
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
Input Supply Range V
HVIN
11 76 V
OSCILLATOR (RTCT)
PWM Frequency f
S
250 kHz
Maximum PWM Duty Cycle D
MAX
47 %
Maximum RTCT Frequency f
RTCTMAX
(Note 12) 1 MHz
RTCT Peak Trip Level V
TH,RTCT
0.51 x V
REGOUT
V
RTCT Valley Trip Level V
TL,RTCT
1V
RTCT Input Bias Current I
IN,RTCT
±1 µA
RTCT Discharge MOSFET
R
DS(ON)
R
DIS,RTCT
Sinking 50mA 35 85 Ω
RTCT Discharge Pulse Width 50 ns
LOOK-AHEAD LOGIC (PPWM)
PPWM to Output Propagation
Delay
t
PPWM
V
PPWM
rising to V
XFRMRL
falling 110 ns
PPWM Output High V
OH,PPWM
Sourcing 2mA 7.0
11.0
V
PPWM Output Low V
OL,PPWM
Sinking 2mA 0.2 V
PWM COMPARATOR (OPTO, RAMP, RCFF)
Common-Mode Input Range V
CM_PWM
0 5.5 V
Input Offset Voltage 10 mV
Input Bias Current -2 +2 µA
RAMP to XFRMRL Propagation
Delay
t
COMPARATOR
From V
RAMP
(50mV overdrive) rising to
V
XFRMRL
rising
100 ns
Minimum OPTO Voltage V
CSS
= 0V, OPTO sinking 2mA
1.47
V
Minimum RCFF Voltage RCFF sinking 2mA
2.18
V
REGOUT LDO (REGOUT)
INBIAS unconnected,
V
HVIN
= 11V to 76V
8.3
8.75
9.2
REGOUT Voltage Set Point V
REGOUT
V
INBIAS
= V
HVIN
= 11V to 76V 9.5
10.6 11.0
V
INBIAS unconnected, V
HVIN
= 15V,
I
REGOUT
= 0 to 30mA
0.25
REGOUT Load Regulation
V
INBIAS
= V
HVIN
= 15V,
I
REGOUT
= 0 to 30mA
0.25
V
INBIAS unconnected, I
REGOUT
= 30mA
1.25
REGOUT Dropout Voltage
V
INBIAS
= V
HVIN
, I
REGOUT
= 30mA
1.25
V
REGOUT Undervoltage
Lockout Threshold
REGOUT rising 6.6 7.0 7.4 V
REGOUT Undervoltage
Lockout Threshold Hysteresis
REGOUT falling 0.7 V
MAX5953A/MAX5953B/MAX5953C/MAX5953D
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)
(All voltages referenced to GND, unless otherwise noted. V
HVIN
= +48V, C
INBIAS
= 1µF, C
REGOUT
= 2.2µF, R
RTCT
= 25kΩ, C
RTCT
=
100pF, C
BST
= 0.22µF, V
CSS
= V
CS
= 0V, V
RAMP
= V
DCUVLO
= 3V, T
J
= 0°C to +125°C, unless otherwise noted. Typical values are at
T
J
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS
MIN
TYP
MAX
UNITS
SOFT-START (CSS)
Soft-Start Current I
CSS
V
CSS
= 0V 33 µA
INTEGRATING FAULT PROTECTION
FLTINT Source Current I
FLTINT
80 µA
FLTINT Trip Point V
FLTINT
rising 2.7 V
FLTINT Hysteresis
0.75
V
INTERNAL POWER FETs
On-Resistance
R
ON
,
POWER
V
DRVIN
= V
BST
= 9V,
V
XFRMRH
= V
SRC
= 0V, I
DS
= 50mA
0.4 0.8 Ω
Off-State Leakage Current -5
+10
µA
Total Gate Charge Per Power
FET
15 nC
HIGH-SIDE DRIVER
Low to High Latency t
LH-HS
Driver delay until FET V
GS
reaches 0.9 x
(V
BST
- V
XFRMRH
) and is fully on
80 ns
High to Low Latency t
HL-HS
Driver delay until FET V
GS
reaches 0.1 x
(V
BST
- V
XFRMRH
) and is fully off
40 ns
Output Drive Voltage V
BST
BST to XFRMRH with high side on 8 V
LOW-SIDE DRIVER
Low to High Latency t
LH-LS
Driver delay until FET V
GS
reaches 0.9 x
V
DRVIN
and is fully on
80 ns
High to Low Latency t
HL-LS
Driver delay until FET V
GS
reaches 0.1 x
V
DRVIN
and is fully off
40 ns
CURRENT-LIMIT COMPARATOR (CS)
Current-Limit Threshold
Voltage
V
ILIM
140
156
172
mV
Current-Limit Input Bias
Current
I
BILIM
0 < V
CS
< 0.3V -2 +2 µA
Propagation Delay to XFRMRL
t
dILIM
From V
CS
rising (10mV overdrive) to
V
XFRMRL
rising
160 ns
BOOST VOLTAGE CIRCUIT (See Figure 9, QB)
Driver Output Delay t
PPWMD
200 ns
One-Shot Pulse Width t
PWQB
300 ns
QB R
DSON
Sinking 20mA 30 60 Ω
THERMAL SHUTDOWN
Shutdown Temperature T
SH
Temperature rising
+160
°C
Thermal Hysteresis T
H
20 °C
MAX5953A/MAX5953B/MAX5953C/MAX5953D
IEEE 802.3af PD Interface and PWM Controllers
with Integrated Power MOSFETs
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (DC-DC Controller) (continued)
(All voltages referenced to GND, unless otherwise noted. V
HVIN
= +48V, C
INBIAS
= 1µF, C
REGOUT
= 2.2µF, R
RTCT
= 25kΩ, C
RTCT
=
100pF, C
BST
= 0.22µF, V
CSS
= V
CS
= 0V, V
RAMP
= V
DCUVLO
= 3V, T
J
= 0°C to +125°C, unless otherwise noted. Typical values are at
T
J
= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS
UNDERVOLTAGE LOCKOUT (DCUVLO)
Threshold Voltage
V
REF
,
DCUVLO
V
DCUVLO
rising
1.14 1.26 1.38
V
Hysteresis
V
HYS
,
DCUVLO
140 mV
Input Bias Current I
IN,DCUVLO
V
DCUVLO
= 3V
-100 +100
nA
SUPPLY CURRENT
From V
HVIN
= 11V to 76V,
V
CSS
= 0V, V
INBIAS
= 11V
0.7 1.5
From V
INBIAS
= 11V to 76V,
V
CSS
= 0V, V
HVIN
= 76V
4.4 6.4
Supply Current
From V
HVIN
= 76V, V
OPIO
= 4V 7
mA
Standby Supply Current V
DCUVLO
= 0V 1 mA
Note 1: Limits at 0°C are guaranteed by design, unless otherwise noted.
Note 2: The input offset current is illustrated in Figure 1.
Note 3: Effective differential input resistance is defined as the differential resistance between V+ and V
EE
without any external
resistance.
Note 4: Classification current is turned off whenever the IC is in power mode.
Note 5: See Table 2 in the Classification Mode section. R
DISC
and R
RCLASS
must be 1%, 100ppm or better. I
CLASS
includes the IC
bias current and the current drawn by R
DISC
.
Note 6: See the Thermal Dissipation section.
Note 7: When UVLO is connected to the midpoint of an external resistor-divider with a series resistance of 25.5kΩ (±1%), the turn-
on threshold set point for the power mode is defined by the external resistor-divider. Make sure the voltage on UVLO does
not exceed its maximum rating of 8V when V
IN
is at the maximum voltage.
Note 8: When V
UVLO
is below V
TH,G,UVLO
, the MAX5953A/MAX5953C set the turn-on voltage threshold internally (V
UVLO,ON
).
Note 9: An input voltage or V
UVLO
glitch below their respective thresholds shorter than or equal to t
OFF_DLY
does not cause the
MAX5953A/MAX5953B/MAX5953C/MAX5953D to exit power-on mode (as long as the input voltage remains above an
operable voltage level of 12V).
Note 10: Guaranteed by design, not tested in production for MAX5953B/MAX5953D.
Note 11: PGOOD references to OUT while PGOOD references to V
EE
.
Note 12: Output switching frequency is
1
/
2
oscillator frequency.
Figure 1. Effective Differential Input Resistance/Offset Current
I
IN
I
INi + 1
I
INi
I
OFFSET
dR
i
1VV
INi
V
INi + 1
I
OFFSET
≅ I
INi
-
V
INi
dR
i
dR
i
≅
(V
INi + 1
- V
INi
)
=
1V
(I
INi + 1
- I
INi
)
(I
INi + 1
- I
INi
)
V
IN
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

MAX5953DUTM+T

Mfr. #:
Buy MAX5953DUTM+T
Manufacturer:
Maxim Integrated
Description:
Switching Controllers IEEE 802.3af PD Int & PWM Controlle
Lifecycle:
New from this manufacturer.
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