MC100EPT22
www.onsemi.com
5
Figure 3. Typical Phase Noise Plot at
f
carrier
= 25 MHz
Figure 4. Typical Phase Noise Plot at
f
carrier
= 156.25 MHz
The above phase noise plots captured using Agilent
E5052A show additive phase noise of the MC100EPT22
device at frequencies 25 MHz and 156.25 MHz respectively
at an operating voltage of 3.3 V in room temperature. The
RMS Phase Jitter contributed by the device (integrated
between 12 kHz and 20 MHz; as shown in the shaded region
of the plot) at each of the frequencies is 158 fs and 48 fs
respectively. The input source used for the phase noise
measurements is Agilent E8663B.
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
− Termination of ECL Logic Devices)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
− 2.0 V
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
