RHYTHM SB3229
www.onsemi.com
5
Table 3. I
2
C TIMING
Parameter Symbol
Standard Mode Fast Mode
Units
Min Max Min Max
Clock Frequency f
PC_CLK
0 100 0 400 kHz
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
t
HD;STA
4.0 − 0.6 −
msec
LOW Period of the PC_CLK Clock t
LOW
4.7 − − −
msec
HIGH Period of the PC_CLK Clock t
HIGH
4.0 − − −
msec
Set−up time for a repeated START condition t
SU;STA
4.7 − − −
msec
Data Hold Time:
for CBUS Compatible Masters
for I
2
C−bus Devices
t
HD;DAT
5.0
0
(Note 1)
−
3.4
(Note 2)
−
0
(Note 1)
−
0.9
(Note 2)
msec
Data set−up time t
SU;DAT
250 − 100 − nsec
Rise time of both PC_SDA and PC_CLK signals t
r
− 1000 20 + 0.1 C
b
(Note 4)
300 nsec
Fall time of both PC_SDA and PC_CLK signals t
f
− 300 20 + 0.1 C
b
(Note 4)
300 nsec
Set−up time for STOP condition t
SU;STO
4.0 − 0.6 − nsec
Bus free time between a STOP and START condition t
BUF
4.7 − 1.3 −
msec
Output fall time from V
IHmin
to V
ILmax
with a bus
capacitance from 10 pF to 400 pF
t
of
− 250 20 + 0.1 C
b
(Note 4)
250 nsec
Pulse width of spikes which must be suppressed by
the input filter
t
SP
n/a n/a 0 50 nsec
Capacitive load for each bus line C
b
− 400 − 400 pF
1. A device must internally provide a hold time of at least 300 ns for the PC_SDA signal to bridge the undefined region of the falling edge of PC_CLK.
2. The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the PC_CLK signal.
3. A Fast−mode I
2
C−bus device can be used in a Standard−mode I
2
C−bus system, but the requirement t
SU;DAT
P250ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the PC_CLK signal. If such a device does stretch the
LOW period of the PC_CLK signal, it must output the next data bit to the PC_SDA line t
r
max + t
SU;DAT
= 1000 + 250 = 1250 ns (according
to the Standard−mode I
2
C−bus specification) before the PC_CLK line is released.
4. C
b
= total capacitance of one bus line in pF.
