4
Sheet No.: D2-A08602EN
PC412S0NIP0F Series
(Unless otherwise specifi ed T
a
=
T
opr
)
Parameter Symbol Rating Unit
Input
Supply voltage V
CC1
0 to 5.5 V
Input voltage V
IN
−
0.5 to V
CC1
+
0.5
V
Output
Supply voltage
V
CC2
0 to 5.5 V
High level output voltage
V
O
−
0.5 to V
CC2
+
0.5
V
Low level output current
I
O
10 mA
*1
Isolation voltage V
iso
(rms) 3.75 kV
Operating temperature T
opr
−
40 to
+
85 ̊C
Storage temperature T
stg
−
55 to
+
125 ̊C
*2
Soldering temperature T
sol
270 ̊C
*1 40 to 60%RH, AC for 1 minute, f
=
60Hz
*2 For 10s
■
Absolute Maximum Ratings
■
Electro-optical Characteristics
(Unless otherwise specifi ed T
a
=
T
opr
, TYP. at T
a
=
25˚C, V
CC1
=
V
CC2
=
5V)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Input
Low level supply current I
CC1L
V
IN
=0
−
6.0 10.0 mA
High level supply current I
CC1H
V
IN
=V
CC1
−
0.8 3.0 mA
Input current I
IN
V
CC1
=5V
−
10
−
10
μ
A
Output
High level supply current I
CC2H
V
IN
=5V
−
2.5 9.0 mA
Low level supply current I
CC2L
V
IN
=0
−
2.0 9.0 mA
High level output voltage V
OH
I
O
=−
20
μ
A, V
IN
=
5V 4.4 5.0
−
V
I
O
=−
4mA, V
IN
=
5V 4.0
4.8 −
V
Low level output voltage V
OL
I
O
=
20
μ
A, V
IN
=
0
− 0
0.1 V
I
O
=
400
μ
A, V
IN
=
0
−−
0.1 V
I
O
=
4mA, V
IN
=
0
−
0.5 1.0 V
Transfer
charac
−
teristics
Isolation resistance R
ISO
DC500V, 4060%RH 5×10
10
10
11
−Ω
Floating capacitance C
f
V
=
0, f
=
1MHz
−
1.0
−
pF
Response time
"High
→
Low" propagation delay time
t
PHL
C
L
=
15pF, CMOS Logic level
V
IN
=
0
→
5V
t
r
=
t
f
<1ns
Pulse width 40ns
Duty 50%
−
23 40 ns
"Low
→
High" propagation delay time
t
PLH
−
22 40 ns
Pulse width distortion |t
pHL
-t
pLH
|
Δ
tw
−−
6ns
Propagation delay skew T
PSK
−−
20 ns
Data transfer rate T
−−
25 Mb/s
Rise time t
r
−
4
−
ns
Fall time t
f
−
3
−
ns
Instantaneous common mode
rejection voltage "Outpu : High level"
CM
H
V
IN
=V
CC1
, V
O
>0.8×V
CC2
V
CM
=1kV
10 20
−
kV/
μ
s
Instantaneous common mode
rejection voltage "Outpu : Low level"
CM
L
V
IN
=0, V
O
<0.8V
V
CM
=1kV
−
10
−
20
−
kV/
μ
s
*3 When measuring output and transfer characteristics, connect a by-pass capacitor (0.01
μ
F or more) between V
CC1
(pin
➀
) and GND
1
(pin
➃
), between V
CC2
(pin
➇
) and GND
2
(pin
➄
) near the device.
