R1LV0216BSB
R10DS0051EJ0100 Rev.1.00 Page 13 of
14
2011.03.30
Low Vcc Data Retention Characteristics
Parameter Symbol Min. Typ. Max. Unit Test conditions
*2
V
CC
for data retention V
DR
2.0 - 3.6 V
Vin ≥ 0V
(1) CS# ≥ Vcc-0.2V or
(2) LB# = UB# ≥ Vcc-0.2V,
CS# ≤ 0.2V
- 1
*1
2 μA ~+25°C
- - 3 μA ~+40°C
- - 8 μA ~+70°C
Data retention current I
CCDR
- - 10 μA ~+85°C
Vcc=3.0V, Vin ≥ 0V
(1) CS# ≥ Vcc-0.2V or
(2) LB# = UB# ≥ Vcc-0.2V,
CS# ≤ 0.2V
Chip deselect to data retention time t
CDR
0 - - ns
Operation recovery time t
R
5 - - ms
See retention waveform.
Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (Ta= 25ºC), and not 100% tested.
2. CS# controls address buffer, WE# buffer, OE# buffer, LB# buffer, UB# buffer and Din buffer. If CS# controls
data retention mode, Vin levels (address, WE#, OE#, LB#, UB#, DQ) can be in the high impedance state.
