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VN5050JTR-E
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P31
Electrical sp
ecifications
VN5050J-E
10/31
T
able 8.
Stat
us pin (V
SD
=0V)
Symbol
Parameter
T
est conditions
Min.
Ty
p
.
Max.
Unit
V
ST
A
T
Status l
ow ou
tput
vol
t
a
g
e
I
ST
A
T
= 1.6 mA, V
SD
=0V
0.5
V
I
LST
A
T
Status l
eakage curr
ent
Nor
mal Operation or V
SD
=5V
,
V
ST
A
T
= 5V
10
µA
C
ST
A
T
Status pin input
capacitance
Nor
mal Operation or V
SD
=5V
,
V
ST
A
T
= 5V
100
pF
V
SCL
Status cl
amp v
oltage
I
ST
A
T
= 1mA
I
ST
A
T
= -1mA
5.5
-0.7
7V
V
T
able 9.
Pr
otections
(1)
(1)
To ensure long term reliability
under heavy overload or s
hort circuit conditions, protection and related
diagnostic signals must be used together with a proper
software strategy. If the device
is subjected to
abnormal conditions, this software must limit the
duration and number of activation cycles.
Symbol
Pa
r
a
m
et
e
r
T
est conditions
Min.
Ty
p
.
Max.
Unit
I
limH
DC shor
t circuit current
V
CC
= 13V
5V<V
CC
<36V
13.5
19
26.5
26.5
A
A
I
limL
Shor
t circuit current
during ther
mal cycling
V
CC
= 13V
T
R
<T
j
<T
TSD
7A
T
TSD
Shutdown temperature
150
175
200
°C
T
R
Reset temperature
T
RS
+ 1
T
RS
+ 5
°C
T
RS
Ther
mal reset of
ST
A
TUS
135
°C
T
HYST
Thermal hyster
esis
(T
TSD
-T
R
)
7°
C
t
SDL
Status dela
y in ov
erload
conditions
T
j
>T
TSD
(see
Figure 4
)2
0
µ
s
V
DEMA
G
T
ur
n-Off output voltage
clamp
I
OUT
=2A; V
IN
=0; L=6mH
V
CC
-41
V
CC
-46
V
CC
-52
V
V
ON
Output voltage drop
limitation
I
OUT
= 0.1A;
T
j
= -40°C
...+1
50°C
(see
Figure 6
)
25
mV
VN5050J-E
Electrical spe
cifications
11/31
T
able 10
.
Openload detection
Symbol
Parameter
T
est conditions
Min.
Ty
p
.
Max.
Unit
I
OL
Openload On State
detection threshold
V
IN
= 5V ,8V<V
CC
<18V
10
See
Figure 18
50
mA
t
DOL(on)
Openload On State
detection delay
I
OUT
= 0A, V
CC
=13V
(see
Figure 4
)
200
µs
t
POL
Dela
y between INPUT
f
alling edge
and ST
A
TU
S
rising edge in Ope
nload
condition
I
OUT
= 0A (see
Figure 4
)
200
500
1000
µs
V
OL
Openload Off State
voltage detection
threshold
V
IN
= 0V
, 8V<V
CC
<16V 2
See
Figure 19
4V
t
DSTK
ON
Output shor
t circuit to
V
CC
detection delay at
turn Off
See
Figure 4
180
t
POL
µs
T
able 11.
Logic input
Symbol
P
arameter
T
est condition
s
Min.
Ty
p
.
Max.
Unit
V
IL
Input low lev
el
0.9
V
I
IL
Low le
v
el Input current
V
IN
=0.9 V
1
µA
V
IH
Input high lev
el
2.1
V
I
IH
High lev
el Input current
V
IN
= 2.1 V
10
µA
V
I(hyst)
Input hysteresis v
oltage
0.25
V
V
ICL
Input clamp voltage
I
IN
= 1mA
I
IN
= -1mA
5.5
-0.7
7V
V
V
SDL
ST
A
T
_DIS low le
v
el
voltage
0.9
V
I
SDL
Low le
v
el ST
A
T_DIS
current
V
SD
= 0.9 V
1
µA
V
SDH
ST
A
T_DIS high level
voltage
2.1
V
I
SDH
High lev
el ST
A
T_DIS
current
V
SD
= 2.1 V
10
µA
V
SD(hyst)
ST
A
T
_DIS h
ysteresis
voltage
0.25
V
V
SDCL
ST
A
T
_DIS clamp voltage
I
SD
=1mA
I
SD
=-1mA
5.5
-0.7
7V
V
Electrical sp
ecifications
VN5050J-E
12/31
Figure 4.
Status timings
Truth Table
T
able 12
.
T
ruth table
Conditions
INPUT
OUTPUT
ST
A
TUS (V
SD
=0V)
(1)
(1)
If the V
SD
is high, the STATUS pin is in a high
impedance.
Nor
mal operation
L
H
L
H
H
H
Current limi
tation
L
H
L
X
H
H
Ov
er
temper
ature
L
H
L
L
H
L
Under
voltage
L
H
L
L
X
X
Output voltage > V
OL
L
H
H
H
Lv
H
Output current < I
OL
L
H
L
H
H
(2)
L
(2)
The STATUS pin becomes hi
gh with a delay equal to t
POL
after INPUT falling edge.
V
IN
V
ST
A
T
t
POL
OPEN LOAD ST
A
TUS TIMING (without ex
ternal pull-up)
I
OUT
< I
OL
V
OUT
< V
OL
t
DOL(on)
V
IN
V
ST
A
T
OPEN LOAD ST
A
TUS TIMING (with external pull-up)
I
OUT
< I
OL
V
OUT
> V
OL
t
DOL(on)
V
IN
V
ST
A
T
O
VER TEMP ST
A
TUS TIMING
t
SDL
t
SDL
T
j
> T
TSD
V
IN
V
ST
A
T
t
DSTKON
OUTPUT STUCK T
O V
CC
I
OUT
> I
OL
V
OUT
> V
OL
t
DOL(on)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P24
P25-P27
P28-P30
P31-P31
VN5050JTR-E
Mfr. #:
Buy VN5050JTR-E
Manufacturer:
STMicroelectronics
Description:
Gate Drivers Sngl Ch HiSide Drivr
Lifecycle:
New from this manufacturer.
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