List of figures VN5050J-E
4/31
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Status low output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. Status leakage current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. On state resistance vs V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. Status clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 18. Openload On state detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 19. Openload Off state voltage detection threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 20. I
LIM
vs T
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 21. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 22. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 23. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 24. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 25. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 26. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 27. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 28. Open load detection in Off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 29. Maximum turn Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. PowerSSO-12™ PC Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 31. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25
Figure 33. Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 34. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 35. PowerSSO-12™ tube shipment (no suffix). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 36. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
VN5050J-E Block diagram and pin description
5/31
1 Block diagram and pin description
Figure 1. Block diagram
Table 2. Pin function
Name Function
V
CC
Battery connection.
OUTPUT Power output.
GND
Ground connection. Must be reverse battery protected by an external diode/resistor
network.
INPUT
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
STATUS Open drain digital diagnostic pin.
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin.
LOGIC
UNDERVOLTAGE
OVERTEMP.
I
LIM
PwCLAMP
GND
INPUT
OUTPUT
DRIVER
V
CC
CLAMP
V
DSLIM
STAT_DIS
STATUS
OPENLOAD ON
OPENLOAD OFF
Pwr
LIM
V
CC
Block diagram and pin description VN5050J-E
6/31
Figure 2. Configuration diagram (top view)
Note: The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The
new pinout is backaward compatible with existing PCB layouts where pins #1 and #6 are
connected to Vcc and/or pins #7 and 12 are connected to OUTPUT. For new PCB designs,
these pins should be left unconnected.
PowerSSO-12
TA B = V
cc
N.C.
OUTPUT
OUTPUT
OUTPUT
N.C.
OUTPUT
12
11
10
9
8
7
1
2
3
4
5
6
N.C.
N.C.
INPUT
STATUS_DIS
GND
STATUS
Table 3. Suggested connections for unused and N.C. pins
Connection / Pin STATUS N.C. OUTPUT INPUT STAT_DIS
Floating X X X X X
To ground N.R.
(1)
(1) Not recommended.
XN.R.
Through 10K
resistor
Through 10K
resistor

VN5050JTR-E

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Gate Drivers Sngl Ch HiSide Drivr
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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