TPS2399DMT7G Datasheet TPS2399DMT7G, TPS2398DMT7G | P10-P12

TPS2398, TPS2399

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APPLICATIONS INFORMATION

General

When a plug−in module or printed circuit card is inserted

into a live chassis slot, discharged supply bulk capacitance

on the board can draw huge transient currents from the

system supplies. Without some form of inrush limiting,

these currents can reach peak magnitudes ranging up to

several hundred amps, particularly in high−voltage systems.

Such large transients can damage connector pins, PCB etch,

and plug−in and supply components. In addition, current

spikes can cause voltage droops on the power distribution

bus, causing other boards in the system to reset.

The TPS2398 and TPS2399 are hot swap power managers

designed to limit these peaks to preset levels, as well as

control the slew rate (di/dt) at which charging current ramps

to the user−programmed limit. These devices use an external

N−channel pass FET and sense element to provide

closed−loop control of current sourced to the load. Input

supply under−voltage lockout (UVLO) protection allows

hot swap circuits to turn on automatically with the

application of power, or to be controlled with a system

command via the EN input. External capacitors control both

the current ramp rate, and the time−out period for load

voltage ramping. In addition, an internal overload

comparator provides circuit breaker protection against

shorts occurring during steady−state (post−turn−on)

operation of the card.

The TPS2398 and TPS2399 operate directly from the

input supply (nominal −48 VDC rail). The –VIN pin

connects to the negative voltage rail, and the RTN pin

connects to the supply return. Internal regulators convert

input power to the supply levels required by the device

circuitry. An input UVLO circuit holds the GATE output low

until the supply voltage reaches a nominal 30 V level. A

second comparator monitors the EN input; this pin must be

pulled above the 1.4 V enable threshold to turn on power to

the load.

Once enabled, and when the input supply is above the

UVLO threshold, the GATE pull−down is removed, the

linear control amplifier (LCA) is enabled, and a large

discharge device in the RAMP CONTROL block is turned

off. Subsequently, a small current source is now able to

charge an external capacitor connected to the IRAMP pin.

This results in a linear voltage ramp at IRAMP. The voltage

ramp on the capacitor actually has two discrete slopes. As

shown in Figure 2, charging current is supplied from either

of two sources. Initially at turn−on, the 600 nA source is

selected, to provide a slow turn−on rate. This slow turn−on

helps ensure that the LCA is pulled out of saturation, and is

slewing to the voltage at its non−inverting input before

normal rate load charging is allowed. This mechanism helps

reduce current steps at turn−on. Once the voltage at the

IRAMP pin reaches approximately 0.5 V, an internal

comparator de−asserts the SLOW signal, and the 10 mA

source is selected for the remainder of the ramp period.

The voltage at IRAMP is divided down by a factor of 100,

and applied to the non−inverting input of the LCA. Load

current magnitude information at the ISENS pin is applied

to the inverting input. This voltage is developed by

connecting the current sense resistor between ISENS and

−VIN. The LCA controls the gate of the external pass FET

to force the ISENS voltage to track the divided down

IRAMP voltage. Consequently, the load current slew rate

tracks the linear voltage ramp at the IRAMP pin, producing

a linear di/dt of the load current. The IRAMP capacitor is

charged to about 5 V; however, the LCA input is clamped at

40 mV. Therefore, the current sourced to the load during

turn−on is limited to a value given by I

MAX

≤ 40 mV / R

SNS

where R

SNS

is the value of the sense resistor.

The resultant load current, regulated by the controller,

charges the module’s input bulk capacitance in a safe

fashion. Under normal conditions, this capacitance

eventually charges up to the dc input potential. At this point,

the load demand drops off, and the voltage at ISENS

decreases. The LCA now drives the GATE output to its

supply rail.

The device detects this condition as the GATE voltage

rises through 7.5 V, latches this status and asserts the /PG

output. If the full sourced current limit is not yet available to

the load, as evidenced by the IRAMP voltage being less than

5 V, then the /PG assertion is delayed until that condition is

also met.

The peak, steady−state GATE pin output, typically 14 V,

ensures sufficient overdrive to fully enhance the external

FET, while not exceeding the typical 20 V V

rating of

common N−channel power FETs.

Fault timing is accomplished by connecting a capacitor

between the FLTTIME and −VIN pins, allowing

user−programming of the timeout period. Whenever the hot

swap controller is in current control mode as described

above, the LCA asserts an overcurrent indication – OC

signal in the Figure 2. Overcurrent fault timing is inhibited

during the slow turn−on portion of the IRAMP waveform.

However, once the device transitions to the normal rate

current ramp (V

IRAMP

≥ 0.5 V), the external capacitor is

charged by a 50 mA source, generating a voltage ramp at the

FLTTIME pin. If the load voltage ramps successfully, the

fault capacitor is discharged, and load initialization can

begin. However, if the timing capacitor voltage attains the

4 V fault threshold, the LCA is disabled, the pass FET is

rapidly turned off, and the fault is latched. Fault capacitor

charging ceases, and the capacitor is then discharged. In

addition, latching of a fault condition causes rapid discharge

of the IRAMP capacitor. In this manner, the soft−start

function is then reset and ready for the next output enable,

if and when conditions permit.

Subsequent to a plug−in’s start−up, and during the

module’s steady−state operation, load faults that force

current limit operation also initiate fault timing cycles as

TPS2398, TPS2399

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described above. In this case, a fault timeout also clears the

previously latched power good status.

The TPS2398 latches off in response to faults; once a fault

timeout occurs, a large NMOS device is activated to rapidly

discharge the external capacitor, resetting the timer for any

subsequent device reset. The TPS2398 can only be reset by

cycling power to the device, or by cycling the EN input.

In response to a latched fault condition, the TPS2399

enters a fault retry mode, wherein it periodically retries the

load to test for continued existence of the fault. In this mode,

the FLTTIME capacitor is discharged slowly by a about a

0.4 mA constant−current sink. When the voltage at the

FLTTIME pin decays below 0.5 V, the LCA and RAMP

CONTROL circuits are re−enabled, and a normal turn−on

current ramp ensues. Again, during the load charging, the

OC signal causes charging of the FLTTIME capacitor until

the next delay period elapses. The sequential charging and

discharging of the FLTTIME capacitor results in a typical

1% retry duty cycle. If the fault subsides, the timing

capacitor is rapidly discharged, duty−cycle operation stops,

and the /PG output is asserted.

Note that because of the timing inhibit during the initial

slow ramp period, the duty cycle in practice is slightly

greater than the nominal 1% value. However, sourced

current during this period peaks at only about one−eighth the

maximum limit. The duty cycle of the normal ramp and

constant−current periods is approximately 1%.

The FAULT LOGIC within the TIMER BLOCK

automatically manages capacitor charge and discharge

actions, and the enabling of the GATE output.

Supply Transient Response

The TPS2398 and TPS2399 also feature a fast−acting

overload comparator which acts to clamp large transients

from catastrophic faults occurring once the pass FET is fully

enhanced, such as short circuits. This function provides a

back−up protection to the LCA by providing a hard gate

discharge action when the LCA is saturated. If sense voltage

excursions above 100 mV are detected, this comparator

rapidly pulls down the GATE output, bypassing the fault

timer, and terminating the short−circuit condition. Once the

spike has been brought down below the overload threshold,

the GATE output is released, allowing the circuit to turn on

again in either current−ramp or current−limit mode. A 4 ms

deglitch filter is applied to the OL signal to help reduce the

occurrence of nuisance trips.

In redundant−supply systems, the sudden switchover to a

supply of higher voltage potential is one more source of

large current spikes. Due to the low impedance of filter

capacitance under such high−frequency transients, these

spikes are generally indistinguishable from true

short−circuit faults to a hot swap controller. However, the

TPS2398 and TPS2399 transient response addresses this

issue by providing rapid circuit−breaker protection for load

faults along with minimal interruption of power flow during

supply switching events. The scope plots in Figure 26

illustrate how.

Figure 26 is a scope capture of the TPS2398/99 response

in a diode−OR configuration to such an input transient event.

(All waveforms are referenced to the −VIN pin.) In this

example, the module is initially operating from a nominal

−43 V supply (relative to the backplane supply return node).

At the first major time division, another power supply, with

an output of −48 V, is suddenly hot swapped into a

secondary, or INB, input. This sudden voltage step is

reflected in the −48V_RTN trace. On this board, the 5 V

potential difference caused an 8 A spike, as shown by the I

trace (I

trace has been measured after the diode−OR). The

GATE pin is rapidly pulled low, which quickly terminates

the overload spike. However, it is quickly released, and seen

to drive back to the pass FET ON−threshold, in this case,

about 5 V. The resultant current−limit operation of the

circuit is evidenced by the 2 A load on the B supply. Once

supply current is flowing again, the filter capacitance is

charged up to the new input supply level, seen here on the

DRAIN

trace. Once the capacitance is fully charged, the

load demand rolls off to the operating 1 A level. As an added

benefit, this event is transparent to the /PG signal, which

remains asserted throughout the disturbance.

Figure 26. Input Transient Response

RTN

(5 V/div, offset 43 V)

IRAMP

(2 V/div)

(2 A/div)

GATE

(5 V/div)

DRAIN

(5 V/div)

/PG

(50 V/div)

IRAMP

= 3.9 nF

FLTTM

= 100 nF

OUT

= 100 mF

OUT

= 50 W

SNS

= 20 W

In order for downstream loads (bricks, etc.) to operate

through the distribution bus transient, it is important to

properly size the filtering capacitance to supply the needed

energy during the OFF−time of the pass FET. In this

example, once the RTN node jumps by 5 V higher than the

original potential, about 6 V develops across the FET,

TPS2398, TPS2399

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indicating approximately a 1 V droop across the brick input.

Therefore, due to the fast response of the TPS2398/99

devices, the 100 mF capacitor achieves excellent hold−up of

the brick input voltage. Actual requirements depend heavily

on the individual application. Whether the device turns back

on in either current−ramp or current−limit mode depends in

part on the size of the ramp capacitor (C

IRAMP

) and the input

capacitance of the pass FET. But in any case, the circuit turns

back on in a controlled−current manner after rapidly

clamping the potentially damaging spike.

Setting the Sense Resistor Value

Due to the current−limiting action of the internal LCA, the

maximum allowable load current for an implementation is

easily programmed by selecting the appropriate sense

resistor value. The LCA acts to limit the sense voltage

ISENS

to its internal reference. Once the voltage at the

IRAMP pin exceeds approximately 4 V, this limit is the

clamp voltage, V

REF_K

. Therefore, a maximum sense

resistor value can be determined from Equation 1.

SNS(MAX)

REF_K(MIN)

MAX

(eq. 1)

SNS(MAX)

33 mV

MAX

Where:

• R

SNS

is the sense resistor value,

• V

REF_K(MIN)

is the minimum ref. clamp voltage, and

• I

MAX

is the desired current limit.

When setting the sense resistor value, it is important to

consider two factors, the minimum current that may be

imposed by the TPS2398 or TPS2399, and the maximum

load under normal operation of the module. For the first

factor, the specification minimum clamp value is used, as

seen in Equation 1. This method accounts for the tolerance

in the sourced current limit below the typical level expected

(40 mV / R

SNS

). (The clamp measurement includes LCA

input offset voltage; therefore, this offset does not have to be

factored into the current limit again.) Second, if the load

current varies over a range of values under normal operating

conditions, then the maximum load level must be allowed

for by the value of R

SNS

. One example of this is when the

load is a switching converter, or brick, which draws higher

input current, for a given power output, when the

distribution bus is at the low end of its operating range, with

decreasing draw at higher supply voltages. To avoid

current−limit operation under normal loading, some margin

should be designed in between this maximum anticipated

load and the minimum current limit level, or

MAX

> I

LOAD(MAX)

, for Equation 1.

For example, using a 20 mW sense resistor for a nominal

1 A load application provides a minimum of 650 mA of

overhead for load variance/margin. Typical bulk capacitor

charging current during turn−on is 2 A (40 mV / 20 mW).

Setting the Inrush Slew Rate

The TPS2398 and TPS2399 devices enable

user−programming of the maximum current slew rate

during load start−up events. A capacitor tied to the IRAMP

pin (C

in the typical application diagram) controls the di/dt

rate. Once the sense resistor value has been established, a

value for ramp capacitor C

IRAMP

, in microfarads, can be

determined from Equation 2.

IRAMP

100 @ R

SNS

MAX

(eq. 2)

Where:

• R

SENSE

is in ohms, and

MAX

•

is the desired maximum slew rate, in

amperes/second.

For example, if the desired slew rate for the typical

application shown is 1500 mA/ms, the calculated value for

IRAMP

is about 3.7 nF. Selecting the next larger standard

value of 3.9 nF (as shown in the diagram) provides some

margin for capacitor and sense resistor tolerances.

As described earlier in this section, the TPS2398 and

TPS2399 initiate ramp capacitor charging, and

consequently, load current di/dt at a reduced rate. This

reduced rate applies until the voltage on the IRAMP pin is

about 0.5 V. The maximum di/dt rate, as set by Equation 2,

is effective once the device has switched to the 10 mA

charging source.

Setting the Fault Timing Capacitor

The fault timeout period is established by the value of the

capacitor connected to the FLTTIME pin, C

FLTTM

. The

timeout period permits riding out spurious current glitches

and surges that may occur during operation of the system,

and prevents indefinite sourcing into faulted loads swapped

into a live system. However, to ensure smooth voltage

ramping under all conditions of load capacitance and input

supply potential, the minimum timeout should be set to

accommodate these system variables. To do this, a rough

estimate of the maximum voltage ramp time for a

completely discharged plug−in card provides a good basis

for setting the minimum timer delay.

Due to the three−phase nature of the load current at

turn−on, the load voltage ramp potentially has three distinct

phases (compare Figures 3 and 4). This profile depends on

the relative values of load capacitance, input dc potential,

maximum current limit and other factors. The first two

phases are characterized by the two different slopes of the

current ramp; the third phase, if required for bulk

capacitance charging, is the constant−current charging at

MAX

. Considering the two current ramp phases to be one

period at an average di/dt simplifies calculation of the

required timing capacitor.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

TPS2399DMT7G

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Manufacturer:

ON Semiconductor

Description:

Hot Swap Voltage Controllers -48 V HOT SWAP CONTROLLER

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