ILC7083/ILC7084
REV. 1.0.9 1/28/03 5
Operation
The ILC7083/ILC7084 LDO design is based on an advanced
circuit configuration for which patent protection has been
applied. Typically it is very difficult to drive a capacitive out-
put with an amplifier. The output capacitance produces a
pole in the feedback path, which upsets the carefully tailored
dominant pole of the internal amplifier. Traditionally the
pole of the output capacitor has been “eliminated” by reduc-
ing the output impedance of the regulator such that the pole
of the output capacitor is moved well beyond the gain band-
width product of the regulator. In practice, this is difficult to
do and still maintain high frequency operation. Typically the
output impedance of the regulator is not simply resistive,
such that the reactive output impedance interacts with the
reactive impedance of the load resistance and capacitance.
In addition, it is necessary to place the dominant pole of
the circuit at a sufficiently low frequency such that the gain
of the regulator has fallen below unity before any of the
complex interactions between the output and the load occur.
The ILC7083/ILC7084 does not try to eliminate the output
pole, but incorporates it into the stability scheme. The load
and output capacitor forms a pole, which rolls off the gain of
the regulator below unity. In order to do this the output
impedance of the regulator must be high, looking like a
current source. The output stage of the regulator becomes a
transconductance amplifier, which converts a voltage to a
current with a substantial output impedance. The circuit
which drives the transconductance amplifier is the error
amplifier, which compares the regulator output to the band
gap reference and produces an error voltage as the input to
the transconductance amplifier. The error amplifier has a
dominant pole at low frequency and a “zero” which cancels
out the effects of the pole. The zero allows the regulator
to have gain out to the frequency where the output pole
continues to reduce the gain to unity. The configuration of
the poles and zero are shown in Figure 1. Instead of power-
ing the critical circuits from the unregulated input voltage,
the CMOS RF LDO powers the internal circuits such as the
bandgap, the error amplifier and most of the transconduc-
tance amplifier from the boot strapped regulated output
voltage of the regulator. This technique offers extremely high
ripple rejection and excellent line transient response.
Figure 1. ILC7083/ILC7084 RF LDO Frequency Response
A block diagram of the regulator circuit used in the ILC7083
is shown in Figure 2, which shows the input-to-output isola-
tion and the cascaded sequence of amplifiers that implement
the pole-zero scheme outlined above.
The ILC7083/ILC7084 is designed in a CMOS process with
some minor additions, which allow the circuit to be used at
input voltages up to 13V. The resulting circuit exceeds the
frequency response of traditional bipolar circuits. The
ILC7083/ILC7084 is very tolerant of output load conditions
with the inclusion of both short circuit and thermal overload
protection. The device has a very low dropout voltage,
typically a linear response of 1mV per milliamp of load
current, and none of the quasi-saturation characteristics of a
bipolar output devices. All the good features of the frequency
response and regulation are valid right to the point where the
regulator goes out of regulation in a 4 millivolt transition
region. Because there is no base drive, the regulator is
capable of providing high current surges while remaining in
regulation. This is shown in the high peak current of 500mA
which allows for the ILC7083/ILC7084 to be used in
systems that require short burst mode operation.
DOMINANT POLE
OUTPUT POLE
85 dB
COMPENSATING
ZERO
UNITY GAIN
FREQUENCY
GAIN
