ILC7083/ILC7084
REV. 1.0.9 1/28/03 7
Maximum Output Current
The maximum output current available from the ILC7083/
ILC7084 is limited by the maximum package power dissipa-
tion as well as the device’s internal current limit. For a given
ambient temperature, TA, the maximum package power
dissipation is given by:
P
D(MAX)
= (T
J(MAX)
– T
A
) / θ
JA
where T
J(MAX)
= 150°C is the maximum junction tempera-
ture and θ
JA
= 333°C/W is the package thermal resistance.
For example at T
A
= 85°C ambient temperature, the maxi-
mum package power dissipation is;
P
D(MAX)
= 195mW.
The maximum output current can be calculated from the fol-
lowing equation:
I
OUT(MAX)
< P
D(MAX)
/ (V
IN
V
OUT
)
For example at V
IN
= 6V, V
OUT
= 5V and T
A
= 85°C, the
maximum output current is I
OUT(MAX)
< 195mA. At higher
output current, the die temperature will rise and cause the
thermal protection circuit to be enabled.
Application Hints
Figure 4 shows the typical application circuit for the
ILC7083.
Figure 4. Basic Application Circuit for
Fixed Output Voltage Versions
Input Capacitor
An input capacitor C
IN
of value 1µF or larger should be con-
nected from V
IN
to the main ground plane. This will help to
filter supply noise from entering the LDO. The input capaci-
tor should be connected as close to the LDO regulator input
pin as is practical. Using a high-value input capacitor will
offer superior line transient response as well as better power
supply ripple rejection. A ceramic or tantalum capacitor may
be used at the input of the LDO regulator.
Note that there is a parasitic diode from the LDO regulator
output to the input. If the input voltage swings below the reg-
ulator’s output voltage by a couple of hundred millivolts then
the regulator may be damaged. This condition must be
avoided. In many applications a large value input capacitor,
C
IN
, will hold V
IN
higher than V
OUT
and decay slower than
V
OUT
when the LDO is powered off.
Output Capacitor Selection
Fairchild strongly recommends the use of low ESR
(equivalent series resistance) ceramic capacitors for C
OUT
and C
NOISE
. The ILC7083/ILC7084 is stable with low ESR
capacitor (as low as zero ). The value of the output
capacitor should be 1µF or higher. Either ceramic chip or
a tantalum capacitor may be used at the output.
Use of ceramic chip capacitors offer significant advantages
over tantalum capacitors. A ceramic capacitor is typically
cheaper than a tantalum capacitor, it usually has a smaller
footprint, lower height, and lighter weight than a tantalum
capacitor. Furthermore, unlike tantalum capacitors which are
polarized and can be damaged if connected incorrectly,
ceramic capacitors are non-polarized. Low value ceramic
chip capacitors with X5R or X7R dielectric are available in
the 100pF to 4.7µF range. Beware of using ceramic capaci-
tors with Y5V dielectric since their ESR increases signifi-
cantly at cold temperatures. Please see the table of
recommended ceramic capacitors for use at the output of
ILC7083/ILC7084.
Note: If a tantalum output capacitor is used then for stable
operation. We recommend a low ESR tantalum capacitor
with maximum rated ESR at or below 0.4. Low ESR tanta-
lum capacitors, such as the TPS series from AVX Corpora-
tion (www.avxcorp.com) or the T495 series from Kemet
(www.kemet.com) may be used.
In applications where a high output surge current can be
expected, use a high value but low ESR output capacitor for
superior load transient response. The ILC7083/ILC7084 is
stable with no load.
Noise Bypass Capacitor
In low noise applications, the self noise of the ILC7083 can
be decreased further by connecting a capacitor from the
noise bypass pin (pin 4) to ground (pin 2). The noise bypass
pin is a high impedance node as such care should be taken in
printed circuit board layout to avoid noise pick-up from
external sources. Moreover, the noise bypass capacitor
should have low leakage.
Noise bypass capacitors with a value as low as 470pF may
be used. However, for optimum performance, use a 0.01µF
or larger, ceramic chip capacitor. Note that the turn on and
turn off response of the ILC7083 is inversely proportional to
the value of the noise bypass capacitor. For fast turn on and
turn off, use a small value noise bypass capacitor. In applica-
tions where exceptionally low output noise is not required,
consider omitting the noise bypass capacitor altogether.
ILC7083
V
OUT
V
IN
C
OUT
SOT23-5
C
IN
ON
OFF
123
45
C
NOISE
ILC7083/ILC7084
8 REV. 1.0.9 1/28/03
The Effects of ESR (Equivalent Series
Resistance)
The ESR of a capacitor is a measure of the resistance due to
the leads and the internal connections of the component.
Typically measured in m (milli-ohms) it can increase to
ohms in some cases.
Wherever there is a combination of resistance and current,
voltages will be present. The control functions of LDOs use
two voltages in order to maintain the output precisely; V
OUT
and V
REF
.
With reference to the block diagram in Figure 4, V
OUT
is fed
back to the error amplifier and is used as the supply voltage
for the internal components of the ILC7083/ILC7084. So
any change in V
OUT
will cause the error amplifier to try to
compensate to maintain V
OUT
at the set level and noise on
V
OUT
will be reflected into the supply of each internal
components of the ILC7083/ILC7084. So any change in
V
OUT
will cause the error amplifier to try to compensate to
maintain V
OUT
at the set level and noise on V
OUT
will be
reflected into the supply of each internal circuit. The refer-
ence voltage, V
REF
, is influenced by the C
NOISE
pin. Noise
into this pin will add to the reference voltage and be fed
through the circuit. These factors will not cause a problem if
some simple steps are taken. Figure 5 shows where these
added ESR resistances are present in the typical LDO circuit.
Figure 5. ESR Present in C
OUT
and C
NOISE
With this in mind low ESR components will offer better
performance where the LDO may be subjected to large load
transients current. ESR is less of a problem with C
IN
as the
voltage fluctuations at the input will be filtered by the LDO.
However, being aware of these current flows, there is also
another potential source of induced voltage noise from the
resistance inherent in the PCB trace. Figure 6 shows where
the additive resistance of the PCB can manifest itself. Again
these resistances may be very small, but a summation of
several currents can develop detectable voltage ripple and
will be amplified by the LDO. Particularly the accumulation
of current flows in the ground plane can develop significant
voltages unless care is taken. With a degree of care, the
ILC7083/ILC7084 will yield outstanding performance.
Printed Circuit Board Layout Guidelines
As was mentioned in the previous section, to take full advan-
tage of any high performance LDO regulator requires paying
careful attention to grounding and printed circuit board
(PCB) layout.
Figure 6. Inherent PCB resistance
Figure 7 shows the effects of poor grounding and PCB
layout magnified by the ESR and PCB resistances and
the accumulation of current flows.
Note that particularly during high output load current, the
LDO regulator’s ground pin and the ground return for C
OUT
and C
NOISE
are not at the same potential as the system
ground. This is due to high frequency impedance caused by
PCB’s trace inductance and DC resistance. The current loop
between C
OUT
, C
NOISE
and the LDO regulator’s ground pin
will degrade performance of the LDO.
Figure 8 shows an optimum schematic. In this schematic,
high output surge current has little effect on the ground cur-
rent and noise bypass current return of the LDO regulator.
Note that the key difference here is that C
OUT
and C
NOISE
are
directly connected to the LDO regulator’s ground pin. The
LDO is then separately connected to the main ground plane
and returned to a single point system ground.
The layout of the LDO and its external components are also
based on some simple rules to minimize EMI and output
voltage ripple.
ILC7083
V
IN
SOT-23-5
C
IN
ON
OFF
123
4
5
C
NOISE
RF LDO
TM
Regulator
R*
R*
R
C
V
OUT
C
OUT
I
C
I
OUT
ILC7083
SOT-23-5
ON
OFF
123
4
5
C
NOISE
R
PCB
ESR
R
PCB
V
IN
C
IN
I
OUT
C
OUT
I
1
ESR
V
OUT
R
PCB
R
PCB
ILC7083/ILC7084
REV. 1.0.9 1/28/03 9
Figure 7. Effects of Poor Circuit Layout
Figure 8. Recommended Application Circuit Schematic
Figure 9. Recommended Application Circuit Layout (not drawn to scale)
Note, ground plane is bottom layer of PCB and connects to top layer ground connections through vias.
321
5
4
V
OUT
I
LOAD
GND5GND1
I
LOAD
C
IN
V
IN
GND2
GND
+IC
OUT
+IC
NOISE
+IGND
ON/OFF
C
NOISE
LOAD
ILC7083
SOT-23-5
GND3
+IC
OUT
+IC
NOISE
C
OUT
I
LOAD
+IC
OUT
GND4
I
LOAD
True GND
(0V)
IC
OUT
C
NOISE
45
12
3
Ground Plane
Ground PlaneGround Plane
Ground Plane
V
BATT
+
GND
DC/DC
Converter
V
IN
C
IN
C
NOISE
V
OUT
ON/OFF
Local
Ground
C
OUT
ESR<0.5
ILC7083
SOT-23-5
LOAD
Fairchild Semiconductor - Eval. Board

ILC7083AIM530X

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG LINEAR 3V 150MA SOT23-5
Lifecycle:
New from this manufacturer.
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