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3308J–FLASH–4/05
AT49BV322A(T)
4.6 VPP Pin
The circuitry of the AT49BV322A(T) is designed so that the device cannot be programmed or
erased if the V
PP
voltage is less that 0.4V. When V
PP
is at 0.9V or above, normal program and
erase operations can be performed. The VPP pin cannot be left floating.
4.7 Program/Erase Status
The device provides several bits to determine the status of a program or erase operation: I/O2,
I/O3, I/O5, I/O6 and I/O7. The “Status Bit Table” on page 12 and the following four sections
describe the function of these bits. To provide greater flexibility for system designers, the
AT49BV322A(T) contains a programmable configuration register. The configuration register
allows the user to specify the status bit operation. The configuration register can be set to one of
two different values, “00” or “01”. If the configuration register is set to “00”, the part will automati-
cally return to the read mode after a successful program or erase operation. If the configuration
register is set to a “01”, a Product ID Exit command must be given after a successful program or
erase operation before the part will return to the read mode. It is important to note that whether
the configuration register is set to a “00” or to a “01”, any unsuccessful program or erase opera-
tion requires using the Product ID Exit command to return the device to read mode. The default
value (after power-up) for the configuration register is “00”. Using the four-bus cycle Set Config-
uration Register command as shown in the “Command Definition Table” on page 13, the value
of the configuration register can be changed. Voltages applied to the RESET
pin will not alter the
value of the configuration register. The value of the configuration register will affect the operation
of the I/O7 status bit as described below.
4.7.1 Data
Polling
The AT49BV322A(T) features Data
Polling to indicate the end of a program cycle. If the status
configuration register is set to a “00”, during a program cycle an attempted read of the last
byte/word loaded will result in the complement of the loaded data on I/O7. Once the program
cycle has been completed, true data is valid on all outputs and the next cycle may begin. During
a chip or sector erase operation, an attempt to read the device will give a “0” on I/O7. Once the
program or erase cycle has completed, true data will be read from the device. Data
Polling may
begin at any time during the program cycle. Please see “Status Bit Table” on page 12 for more
details.
If the status bit configuration register is set to a “01”, the I/O7 status bit will be low while the
device is actively programming or erasing data. I/O7 will go high when the device has completed
a program or erase operation. Once I/O7 has gone high, status information on the other pins can
be checked.
The Data
Polling status bit must be used in conjunction with the erase/program and V
PP
status
bit as shown in the algorithm in Figures 4-1 and 4-2 on page 10.
4.7.2 Toggle Bit
In addition to Data
Polling the AT49BV322A(T) provides another method for determining the end
of a program or erase cycle. During a program or erase operation, successive attempts to read
data from the memory will result in I/O6 toggling between one and zero. Once the program cycle
has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may
begin at any time during a program cycle. Please see “Status Bit Table” on page 12 for more
details.
The toggle bit status bit should be used in conjunction with the erase/program and V
PP
status bit
as shown in the algorithm in Figures 4-3 and 4-3 on page 11.
