2004 Oct 15 7
Philips Semiconductors Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
DC CHARACTERISTICS
Over recommended operating conditions; voltages are referenced to GND (ground=0V).
Notes
1. All typical values are measured at V
CC
= 3.3 V and T
amb
=25°C.
2. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
3. Unused pins at V
CC
or GND.
4. This is the bus hold overdrive current required to force the input to the opposite logic state.
5. This parameter is valid for any V
CC
between 0 V and 1.2 V with a transition time of up to 10 ms. From V
CC
= 1.2 V
to V
CC
= 3.3 V ± 0.3 V a transition time of 100 µs is permitted. This parameter is valid for T
amb
=25°C only.
6. I
CCZ
is measured with outputs pulled to V
CC
or GND.
7. This is the increase in supply current for each input at the specified voltage level other than V
CC
or GND.
SYMBOL PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX. UNIT
OTHER V
CC
(V)
T
amb
= 40 °C to +85 °C
V
IK
input clamp voltage I
IK
= 18 mA 2.7 −−0.85 1.2 V
V
OH
HIGH-level output voltage I
OH
= 32 mA 3.0 2.0 2.3 V
V
OL
LOW-level output voltage I
OL
=64mA 3.0 0.4 0.55 V
V
RST
power-up output LOW
voltage
I
O
= 1 mA; V
I
= GND or V
CC
;
note 2
3.6 0.1 0.55 V
I
LI
input leakage current V
I
=V
CC
or GND; control pins 3.6 0.1 ±1 µA
V
I
= 5.5 V 0 or 3.6 0.4 10 µA
V
I
=V
CC
; data pins; note 3 3.6 0.1 1 µA
V
I
= 0 V; data pins; note 3 3.6 −−0.4 5 µA
I
off
output OFF current V
I
or V
O
=0Vto4.5V 0 0.1 ±100 µA
I
hold
bus hold current D inputs V
I
= 0.8 V; note 4 3.0 75 135 −µA
V
I
= 2.0 V; note 4 3.0 75 135 −µA
V
CC
= 3.6 V; note 4 0 to 3.6 ±500 −−µA
I
EX
current into an output in the
HIGH state when V
O
>V
CC
V
O
= 5.5 V 3.0 50 125 µA
I
pu/pd
power-up/down 3-state
output current
V
O
= 5.5 V to V
CC
;
V
I
= GND or V
CC
; V
OE
= don’t
care; note 5
1.2 V 1 ±100 µA
I
OZH
3-state output HIGH current V
O
= 3.0 V; V
I
=V
IH
or V
IL
3.6 0.5 5 µA
I
OZL
3-state output LOW current V
O
= 0.5 V; V
I
=V
IH
or V
IL
3.6 +0.5 5 µA
I
CCH
quiescent supply current outputs HIGH; I
O
=0A;
V
I
= GND or V
CC
3.6 0.14 0.24 mA
I
CCL
quiescent supply current outputs LOW; I
O
=0A;
V
I
= GND or V
CC
3.6 812mA
I
CCZ
quiescent supply current outputs disabled; I
O
=0A;
V
I
= GND or V
CC
; note 6
3.6 0.14 0.24 mA
I
CC
additional supply current
per input pin
one input at V
CC
0.6 V; other
inputs at GND or V
CC
; note 7
3.0 to 3.6 0.1 0.2 µA
2004 Oct 15 8
Philips Semiconductors Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
AC CHARACTERISTICS
GND = 0 V; t
r
=t
f
2.5 ns; C
L
= 50 pF; R
L
= 500 .
Note
1. All typical values are measured at V
CC
= 3.3 V and T
amb
=25°C.
SYMBOL PARAMETER
CONDITIONS
MIN. TYP.
(1)
MAX. UNIT
WAVEFORMS V
CC
(V)
T
amb
= 40 °C to +85 °C
t
PLH
propagation delay
nCP to nQ
n
see Fig.5 2.7 −−6.2 ns
3.0 to 3.6 1.5 3.0 5.3 ns
t
PHL
propagation delay
nCP to nQ
n
see Fig.5 2.7 −−5.1 ns
3.0 to 3.6 1.5 3.0 4.9 ns
t
PZH
output enable time to
HIGH level
see Figs 7 and 8 2.7 −−6.9 ns
3.0 to 3.6 1.5 3.5 5.6 ns
t
PZL
output enable time to
LOW level
see Figs 7 and 8 2.7 −−6.0 ns
3.0 to 3.6 1.5 3.2 4.9 ns
t
PHZ
output disable time from
HIGH level
see Figs 7 and 8 2.7 −−5.7 ns
3.0 to 3.6 1.5 3.5 5.4 ns
t
PLZ
output disable time from
LOW level
see Figs 7 and 8 2.7 1.5 3.2 5.1 ns
3.0 to 3.6 1.5 3.2 5.0 ns
t
suH
set-up time
nD
n
HIGH to nCP
see Fig.6 2.7 2.0 −−ns
3.0 to 3.6 2.0 0.7 ns
t
suL
set-up time
nD
n
LOW to nCP
see Fig.6 2.7 2.0 −−ns
3.0 to 3.6 2.0 0.7 ns
t
hH
hold time
nD
n
HIGH to nCP
see Fig.6 2.7 0.1 −−ns
3.0 to 3.6 0.8 0 ns
t
hL
hold time
nD
n
LOW to nCP
see Fig.6 2.7 0.1 −−ns
3.0 to 3.6 0.8 0 ns
t
WH
nCP HIGH pulse width see Fig.6 2.7 1.5 −−ns
3.0 to 3.6 1.5 0.6 ns
t
WL
nCP LOW pulse width see Fig.6 2.7 3.0 −−ns
3.0 to 3.6 3.0 1.6 ns
f
max
maximum clock pulse
frequency
see Fig.5 3.0 to 3.6 150 −−MHz
2004 Oct 15 9
Philips Semiconductors Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
AC WAVEFORMS
handbook, full pagewidth
MNA677
nCP input
nQ
n
output
t
PHL
t
PLH
V
M
V
OH
2.7 V
0 V
V
OL
V
M
V
M
1/f
max
Fig.5 Clock (nCP) to output (nQ
n
) propagation delays, the clock pulse width and the maximum clock pulse
frequency.
V
M
= 1.5 V;
V
M
= GND to 3.0 V.
handbook, full pagewidth
MNA678
t
suH
t
suL
t
hH
t
hL
t
WL
t
WH
0 V
2.7 V
V
M
V
M
0 V
2.7 V
nCP input
nD
n
input
Fig.6 Set-up and hold times for inputs (nD
n
) to inputs (nCP).
The shaded areas indicate when the input is permitted to change for predicable output performance.

74LVT32374EC,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Flip Flops 3.3V 32-BIT D-TYPE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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