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PL123E-05HSI

P1-P3P4-P6P7-P9P10-P10
(Preliminary)PL123E-05
Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Page 1
FEATURES
Frequency Range 10MHz to 220MHz
Zero input - output delay.
Low output-to-output skew.
Optional Drive Strength:
Standard (8mA) PL123E-05
High (12mA) PL123E-05H
2.5V or 3.3V, ±10% operation.
Available in 8-pin SOP packaging.
DESCRIPTION
The PL123E-05 (-05H for High Drive) is a high perfor-
mance, low skew, low jitter zero delay buffer d esigned
to distribute high speed clocks. It has five low-skew
outputs that are synchronized with the input. The syn-
chronization is established via CLKOUT feed back to
the input of the PLL. Since the skew between the input
and output is less than 100ps, the device acts as a
zero delay buffer. The input output propagation delay
can be advanced or delayed by adjusting the load on
the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
PIN CONFIGURATION
SOP-8L
BLOCK DIAGRAM
1
2
3
4
REF
5
6
7
8
CLK2
CLK1
GND
CLKOUT
CLK4
VDD
CLK3
PLL
REF CLKOUT
CLK1
CLK2
CLK3
CLK4
(Preliminary)PL123E-05
Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Pa ge 2
PIN DESCRIPTION
Name
Package Type
Type
Description
SOP-8L
REF
[1 ]
1
I
Input reference frequency.
CLK2
[2 ]
2
O
Buffered clock output.
CLK1
[2 ]
3
O
Buffered clock output.
GND
4
P
Ground connection.
CLK3
[2 ]
5
O
Buffered clock output.
VDD
6
P
VDD connection.
CLK4
[2 ]
7
O
Buffered clock output.
CLKOUT
[2 ,3]
8
O
Buffered clock output. Internal feed back on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs.
3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the
skew between the reference and output.
INPUT / OUTPUT SKEW CONTROL
The PL123E-05 will achieve Zero Delay from input to output when all the outputs are loaded equally. Adjus t-
ments to the input/output delay can be made by adjusting the loading on the CLKOUT pin.
Please contact Micrel for more information.
(Preliminary)PL123E-05
Low Skew Zero Delay Buffer
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Pa ge 3
LAYOUT RECOMMENDATIONS
The following guidelines are to assist y ou with a performance optimized PCB design:
Signal Integrity and Termination
Considerations
- Keep traces short!
- Trace = Inductor. With a capacitive load this
equals ringing!
- Long trace = Transmission Line. Without proper
termination this will cause reflections ( looks like
ringing ).
- Design long traces as “striplines” or “microstrips”
with defined impedance.
- Match trace at one side to avoid reflections bounc-
ing back and forth.
Decoupling and Power Supply
Considerations
- Place decoupling capacitors as close as possible to
the VDD pin(s) to limit noise from the power supply
- Addition of a ferrite bead in series with VDD can
help prevent noise from other board sources
- Value of decoupling capacitor is frequency de-
pendant. Typical values to use are 0.1F for de-
signs using frequencies < 50MHz and 0.01F for
designs using frequencies > 50MHz.
P1-P3P4-P6P7-P9P10-P10

PL123E-05HSI

Mfr. #:
Buy PL123E-05HSI
Manufacturer:
Microchip Technology / Micrel
Description:
Clock Buffer Low Skew 1:5 Zero Delay Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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