PL123E-05HSI Datasheet PL123E-05SC-R, PL123E-05HSI, PL123E-05SI | P4-P6

(Preliminary)PL123E-05

Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Pa ge 4

Absolute Maximum Conditions

Supply Voltage to Ground Potential ...... –0.5V to 4.6V

DC Input Voltage............................. V

SS

– 0.5V to 4.6V

Storage Temperature ......................... –65°C to 150°C

Junction Temperature ....................................... 150°C

Static Discharge Voltage

(per MIL-STD-883, Method 3015)………………> 2000V

Operating Condition

Description

Parameter

Min

Max

Unit

Supply Voltage

V

DD

2.25

3.63

V

Load Capacitance, <100 MHz, 3.3V

C

L

[4]

–

30

pF

Load Capacitance, <100 MHz, 2.5V with High Drive

–

30

pF

Load Capacitance, <133.3 MHz, 3.3V

–

22

pF

Load Capacitance, <133.3 MHz, 2.5V with High Drive

–

22

pF

Load Capacitance, <133.3 MHz, 2.5V with Standard Drive

–

15

pF

Load Capacitance, >133.3 MHz, 3.3V

–

15

pF

Load Capacitance, >133.3 MHz, 2.5V with High Drive

–

15

pF

Input Capacitance

[5]

C

IN

–

5

pF

Closed-loop bandwidth (typical), 3.3V

BW

1

MHz

Closed-loop bandwidth (typical), 2.5V

0.5

MHz

Output Impedance (typical), 3.3V Hi gh Drive

R

OU T

23

Ω

Output Impedance (typical), 3.3V Standard Drive

33

Ω

Output Impedance (typical), 2.5V High Drive

26

Ω

Output Impedance (typical), 2.5V Standard Drive

39

Ω

Power-up time for all V

DD

’s to reach minimum specified

voltage (power ramps must be monotonic)

t

PU

0.01

250

ms

Notes:

4. Applies to Test Circuit #1.

5. Applies to both REF Clock and internal feedback path on CLKOUT.

6. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1.

(Preliminary)PL123E-05

Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Pa ge 5

3.3V DC Electrical Specifications

Description

Parameter

Test Conditions

Min

Max

Unit

Supply Voltage

V

DD

2.97

3.63

V

Input LOW Voltage

V

IL

–

0.8

V

Input HIGH Voltage

V

IH

2.5

V

DD

+ 0.3

V

Input Leakage Current

I

IL

0 < V

IN

< V

IL

–

±10

µA

Input HIGH Current

I

IH

V

IN

= V

DD

–

100

µA

Output LOW Voltage

V

OL

I

OL

= 8 mA (Standard Drive)

I

OL

= 12 mA (High Drive)

–

0.4

V

Output HIGH Voltage

V

OH

I

OH

= –8 mA (Standard Drive)

I

OH

= –12 mA (High Drive)

2.4

–

V

Supply Current

I

DD

Unloaded outputs, 66-MHz REF

–

45

mA

2.5V DC Electrical Specifications

Description

Parameter

Test Conditions

Min

Max

Unit

Supply Voltage

V

DD

2.25

2.75

V

Input LOW Voltage

V

IL

–

0.7

V

Input HIGH Voltage

V

IH

1.7

V

DD

+ 0.3

V

Input Leakage Current

I

IL

0<V

IN

< V

DD

–

10

µA

Input HIGH Current

I

IH

V

IN

= V

DD

–

100

µA

Output LOW Voltage

V

OL

I

OL

= 8 mA (Standard Drive)

I

OL

= 12 mA (High Drive)

–

0.5

V

Output HIGH Voltage

V

OH

I

OH

= –8 mA (Standard Drive)

I

OH

= –12 mA (High Drive)

V

DD

– 0.6

V

DD

– 0.6

–

V

Supply Current

I

DD

Unloaded outputs, 66-MHz REF

–

30

mA

(Preliminary)PL123E-05

Low Skew Zero Delay Buffer

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944 -0800 • fax +1(408) 474-1000 • www.micrel.com Rev 12/13/11 Pa ge 6

3.3V and 2.5V AC Electrical Specifications

Description

Parameter

Test Conditions

Min

Typ

Max

Unit

Maximum Frequency

[7]

(Input/Output)

1/t

1

3.3V High Drive

10

–

220

MHz

3.3V Standard Drive

10

–

167

MHz

2.5V High Drive

10

–

200

MHz

2.5V Standard Drive

10

–

134

MHz

Input Duty Cycle

(PLL Mode only)

T

IDC

<133.3 MHz

25

–

75

%

>133.3 MHz

40

–

60

%

Output Duty Cycle

[8 ]

t

2

÷ t

1

<133.3 MHz

47

–

53

%

>133.3 MHz

45

–

55

%

Rise, Fall Time (3.3V)

[8 ]

t

3

,t

4

Standard Drive, CL = 30pF, <100 MHz

–

1.6

–

ns

Standard Drive, CL = 22pF, <133.3 MHz

–

1.6

–

ns

Standard Drive, CL = 15pF, <167 MHz

–

0.6

–

ns

High Drive, CL = 30pF, <100 MHz

–

1.2

–

ns

High Drive, CL = 22pF, <133.3 MHz

–

1.2

–

ns

High Drive, CL = 15pF, >133.3 MHz

–

0.5

–

ns

Rise, Fall Time (2.5V)

[8 ]

t

3

, t

4

Standard Drive, CL = 15pF, <133.33 MHz

–

1.5

–

ns

High Drive, CL = 30pF, <100 MHz

–

2.1

–

ns

High Drive, CL = 22pF, <133.3 MHz

–

1.3

–

ns

High Drive, CL = 15pF, >133.3 MHz

–

1.2

–

ns

Output to Output Skew

[8 ]

t

5

All outputs equally loaded

–

100

ps

Delay, REF Rising Edge

to CLKOUT Rising Edge

[8 ]

t

6

PLL enabled @ 3.3V

–100

–

100

ps

PLL enabled @2.5V

–200

–

200

ps

Part to Part Skew

[8]

t

7

Measured at V

DD

/2.

Any output to any output, 3.3V supply

–

±150

ps

Measured at V

DD

/2.

Any output to any output, 2.5V supply

–

±300

ps

PLL Lock Time

[8 ]

t

LOC K

Stable power supply, valid clocks pre-

sented on REF and CLKOUT pins

–

1.0

ms

Cycle-to-Cycle Jitter,

Peak

[8,9 ]

T

JCC

3.3V, >66 MHz, <15pF

–

55

ps

3.3V, >66 MHz, <30pF, Standard. Drive

–

125

ps

3.3V, >66 MHz, <30pF, High Drive

–

100

ps

2.5V, >66 MHz, <15pF, Standard. Drive

–

100

ps

2.5V, >66 MHz, <15pF, High Drive

–

80

ps

2.5V, >66 MHz, <30pF, High Drive

–

125

ps

PL123E-05HSI

PL123E-05HSI

Products related to this Datasheet