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MC74HC589ADTR2G

P1-P3P4-P6P7-P9P10-P12
© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 7
1 Publication Order Number:
MC74HC589A/D
MC74HC589A
8-Bit Serial or
Parallel-Input/Serial-Output
Shift Register with 3-State
Output
High−Performance Silicon−Gate CMOS
The MC74HC589A device consists of an 8−bit storage latch which
feeds parallel data to an 8−bit shift register. Data can also be loaded
serially (see the Function Table). The shift register output, Q
H
, is a
3−state output, allowing this device to be used in bus−oriented
systems.
The HC589A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC
Standard No. 7 A
• Chip Complexity: 526 FETs or 131.5 Equivalent Gates
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant
Figure 1. Logic Diagram
SERIAL
DATA
INPUT
14
15
1
2
3
4
5
6
7
12
11
13
10
S
A
A
B
C
D
E
F
G
H
LATCH CLOCK
SHIFT CLOCK
SERIAL SHIFT/
PARALLEL LOAD
OUTPUT ENABLE
PARALLEL
DATA
INPUTS
DATA
LATCH
SHIFT
REGISTER
V
CC
= PIN 16
GND = PIN 8
9
Q
H
SERIAL
DATA
OUTPUT
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
MARKING DIAGRAMS
SOIC−16
TSSOP−16
1
16
HC589AG
AWLYWW
HC
589A
ALYWG
G
1
16
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
SERIAL SHIFT/
PARALLEL LOA
D
S
A
A
V
CC
Q
H
OUTPUT
ENABLE
SHIFT CLOCK
E
D
C
B
GND
H
G
F
MC74HC589A
http://onsemi.com
2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) −0.5 ≤ V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) −0.5 ≤ V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±35 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
I
GND
DC Ground Current per Ground Pin ±75 mA
T
STG
Storage Temperature Range −65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature Under Bias +150
_C
q
JA
Thermal Resistance PDIP
SOIC
TSSOP
78
112
148
_C/W
P
D
Power Dissipation in Still Air at 85_C PDIP
SOIC
TSSOP
750
500
450
mW
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
> 4000
> 200
> 1000
V
I
Latchup
Latchup Performance Above V
CC
and Below GND at 85_C (Note 4)
±300 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 )125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
V
CC
= 3.0 V
(Figure 2) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
800
500
400
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
5. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
MC74HC589A
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol Parameter Test Conditions V
−55_C to 25_C ≤ 85_C ≤ 125_C
Unit
V
IH
Minimum High−Level Input
Voltage
V
out
= 0.1 V or V
CC
*0.1 V
|I
out
| ≤ 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V or V
CC
*0.1 V
|I
out
| ≤ 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum High−Level
Output Voltage
V
in
= V
IH
or V
IL
|I
out
| ≤ 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 2.4 mA
|I
out
| ≤ 6.0 mA
|I
out
| ≤ 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
OL
Maximum Low−Level
Output Voltage
V
in
= V
IH
|I
out
| ≤ 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| ≤ 2.4 mA
|I
out
| ≤ 6.0 mA
|I
out
| ≤ 7.8 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage
Current
V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
OZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
6.0 ±0.5 ±5.0 ±10
mA
I
CC
Maximum Quiescent
Supply Current
(per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 4 40 160
mA
P1-P3P4-P6P7-P9P10-P12

MC74HC589ADTR2G

Mfr. #:
Buy MC74HC589ADTR2G
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers 8-Bit 3 State Shift
Lifecycle:
New from this manufacturer.
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