MC74HC589A
http://onsemi.com
7
A−H
50%
50%
LATCH
CLOCK
V
CC
GND
*Includes all probe and jig capacitance.
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
DATA
VALID
t
su
t
h
S
A
50%
50%
SHIFT
CLOCK
V
CC
GND
t
su
t
h
SERIAL SHIFT/
PARALLEL
LOAD
50%
50%
SHIFT
CLOCK
V
CC
GND
t
su
Figure 6. Figure 7.
Figure 8.
Figure 9. Test Circuit
SWITCHING WAVEFORMS
Figure 10. Test Circuit
*Includes all probe and jig capacitance.
C
L
*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
1 kW
DATA
VALID
PIN DESCRIPTIONS
Data Inputs
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
Parallel data inputs. Data on these inputs are stored in the
data latch on the rising edge of the Latch Clock input.
S
A
(Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load
is high. Data on this input is ignored
when Serial Shift/Parallel Load
is low.
Control Inputs
Serial Shift/Parallel Load (Pin 13)
Shift register mode control. When a high level is applied
to this pin, the shift register is allowed to serially shift data.
When a low level is applied to this pin, the shift register
accepts parallel data from the data latch.
Shift Clock (Pin 11)
Serial shift clock. A low−to−high transition on this input
shifts data on the serial data input into the shift register and
data in stage H is shifted out Q
H
, being replaced by the data
previously stored in stage G.
Latch Clock (Pin 12)
Data latch clock. A low−to−high transition on this input
loads the parallel data on inputs A−H into the data latch.
Output Enable (Pin 10)
Active−low output enable A high level applied to this pin
forces the Q
H
output into the high impedance state. A low
level enables the output. This control does not affect the state
of the input latch or the shift register.
Output
Q
H
(Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register. This is a 3−state output.
