LTC3630A
16
3630afc
For more information www.linear.com/LTC3630A
applicaTions inForMaTion
Note that the soft-start capacitor may not be the limiting
factor in the output voltage ramp. The maximum output
current, which is equal to half the peak current, must
charge the output capacitor from 0V to its regulated value.
For small peak currents or large output capacitors, this
ramp time can be significant. Therefore, the output voltage
ramp time from 0V to the regulated V
OUT
value is limited
to a minimum of:
Ramp Time
2 C
OUT
I
PEAK
V
OUT
C
ISET
Selection
Once the peak current resistor, R
ISET
, and inductor are se-
lected to meet
the load current and frequency requirements,
an optional capacitor, C
ISET
, can be added in parallel with
R
ISET
. This will boost efficiency at mid-loads and reduce
the output voltage ripple dependency on load current at the
expense of slightly degraded load step transient response.
The peak inductor current is controlled by the voltage on
the I
SET
pin. Current out of the I
SET
pin isA while the
LTC3630A is switching and is reduced toA during sleep
mode. The I
SET
current will return toA on the first cycle
after sleep mode. Placing a parallel RC from the I
SET
pin to
ground filters the I
SET
voltage as the LTC3630A enters and
exits sleep mode which in turn will affect the output volt-
age ripple
, efficiency and load step transient performance.
In
general, when R
ISET
is greater than 120k a C
ISET
ca-
pacitor in the 100pF to 200pF range will improve most
per
formance parameters. When R
ISET
is less than 100k,
the capacitance on the I
SET
pin should be minimized.
Higher Current Applications
For applications that require more
than 500
mA, the
LTC3630A provides a feedback comparator output pin
(FBO) for driving additional LTC3630As. When the FBO
pin of amaster” LTC3630A is connected to the V
FB
pin
of one or moreslave” LTC3630As, the master controls
the burst cycle of the slaves.
Figure 10 shows an example of a 5V, 1A regulator using
two LTC3630As. The master is configured for a 5V fixed
output with external soft-start and the V
IN
UVLO level is
set by the RUN pin. Since the slaves are directly controlled
V
FB
SW
L1
L2
V
IN
RUN
R3
C
IN
C
OUT
V
OUT
5V
1A
C
SS
V
IN
R4
SS
V
PRG1
V
PRG2
FBO
LTC3630A
(MASTER)
SW
V
FB
V
IN
RUN
SS
V
PRG1
V
PRG2
FBO
3630a F10
LTC3630A
(SLAVE)
I
SET
I
SET
Figure 10. 5V, 1A Regulator
by the master, the SS pin of the slave should have minimal
capacitance and the RUN pin of the slave should be floating.
Furthermore, slaves should be configured for a 1.8V fixed
output (V
PRG1
= V
PRG2
= SS) to set the V
FB
pin threshold at
1.8V. The inductors L1 and L2 do not necessarily have to
be the same, but should both meet the criteria described
above in the Inductor Selection section.
Efficiency Considerations
The efficiency of a switching regulator is equal to the output
power divided by the input power times 100%. It is often
useful to analyze individual losses to determine what is
limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percent
-
age of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of
the losses: V
IN
operating current and I
2
R losses. The V
IN
operating current dominates the efficiency loss at very
low load currents whereas the I
2
R loss dominates the
efficiency loss at medium to high load currents.
1. The
V
IN
operating current comprises two components:
The DC supply current as given in the electrical charac-
teristics and
the internal MOSFET gate charge currents.
LTC3630A
17
3630afc
For more information www.linear.com/LTC3630A
applicaTions inForMaTion
The gate charge current results from switching the gate
capacitance of the internal power MOSFET switches.
Each time the gate is switched from high to low to
high again, a packet of charge, ∆Q, moves from V
IN
to
ground. The resulting ∆Q/dt is the current out of V
IN
that is typically larger than the DC bias current.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
and external inductor R
L
. When
switching, the average output current flowing through
the inductor ischopped” between the high side PMOS
switch and the low side NMOS switch. Thus, the series
resistance looking back into the switch pin is a function
of the top and bottom switch R
DS(ON)
values and the
duty cycle (DC = V
OUT
/V
IN
) as follows:
R
SW
= (R
DS(ON)TOP
)DC + (R
DS(ON)BOT
) • (1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can
be obtained from the Typical Performance Characteris-
tics cur
ves. Thus, to obtain the I
2
R losses, simply add
R
SW
to R
L
and multiply the result by the square of the
average output current:
I
2
R Loss = I
O
2
(R
SW
+ R
L
)
Other losses, including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses, generally account for
less than 2% of the total power loss.
Thermal Considerations
In most applications, the LTC3630A does not dissipate
much heat due to its high efficiency. But, in applications
where the LTC3630A is running at high ambient tempera
-
ture with low supply voltage and high duty cycles, such
as
dropout, the heat dissipated may exceed the maximum
junction temperature of the part.
To prevent the LTC3630A from exceeding the maximum
junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum junc
-
tion temperature
of the part. The temperature rise from
ambient to junction is given by:
T
R
= P
D
θ
JA
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature is given by:
T
J
= T
A
+ T
R
Generally, the worst-case power dissipation is in dropout
at low input voltage. In dropout, the LTC3630A can provide
a DC current as
high as the full 1.2A peak current to the
output.
At low input voltage, this current flows through a
higher resistance MOSFET, which dissipates more power.
As an example, consider the LTC3630A in dropout at an
input voltage of 5V, a load current of 500mA and an ambi
-
ent temperature
of 85°C. From the Typical Performance
graphs of Switch On-Resistance, the R
DS(ON)
of the top
switch at V
IN
= 5V and 100°C is approximately 1.9Ω.
Therefore, the power dissipated by the part is:
P
D
= (I
LOAD
)
2
R
DS(ON)
= (500mA)
2
• 1.9Ω = 0.475W
For the MSOP package the θ
JA
is 45°C/W. Thus, the junc-
tion temperature of the regulator is:
T
J
= 85°C+0.475W
45°C
W
= 106.4°C
which is below the maximum junction temperature of
150°C.
Note that the while the LTC3630A is in dropout, it can
provide output current that is equal to the peak current
of the part. This can increase the chip power dissipation
dramatically and may cause the internal overtemperature
protection circuitry to trigger at 180°C and shut down
the LTC3630A.
Design Example
As a design example, consider using the LTC3630A in an
application with the following specifications: V
IN
= 24V,
V
IN(MAX)
= 80V, V
OUT
= 3.3V, I
OUT
= 500mA, f = 200kHz.
Furthermore, assume for this example that switching
should start when V
IN
is greater than 12V.
First, calculate the inductor value that gives the required
switching frequency:
L =
3.3V
200kHz 1.2A
1
3.3V
24V
10µH
LTC3630A
18
3630afc
For more information www.linear.com/LTC3630A
applicaTions inForMaTion
Next, verify that this value meets the L
MIN
requirement.
For this input voltage and peak current, the minimum
inductor value is:
L
MIN
=
24V 150ns
1.2A
3µH
Therefore, the minimum inductor requirement is satisfied
and the 10μH inductor value may be used.
Next, C
IN
and C
OUT
are selected. For this design, C
IN
should
be sized for a current rating of at least:
I
RMS
= 500mA
3.3V
24V
24V
3.3V
1 175mA
RMS
The value of C
IN
is selected to keep the input from droop-
ing less than 240mV (1%):
C
IN
>
10µH 1.2A
2
2 24V 240mV
2.2µF
C
OUT
will be selected based on a value large enough to
satisfy the output voltage ripple requirement. For a 50mV
output ripple, the value of the output capacitor can be
calculated from:
C
OUT
>
10µH 1.2A
2
2 3.3V 50mV
47µF
C
OUT
also needs an ESR that will satisfy the output voltage
ripple requirement. The required ESR can be calculated
from:
ESR <
50mV
1.2A
40m
A 47µF ceramic capacitor has significantly less ESR than
40mΩ.
Since an output voltage of 3.3V is one of the standard
output configurations, the LTC3630A can be configured
by connecting V
PRG1
to ground and V
PRG2
to the SS pin.
The undervoltage lockout requirement on V
IN
can be satis-
fied with a resistive divider from V
IN
to the RUN pin (refer
to Figure 9). Calculate R3 and R4 as follows:
R3 = 200kwhichis
12V
40µA
R4 =
200k 1.21V
12V 1.21V +200k 4µA
= 20.9k
Choose standard values for R3 = 200k, R4 = 21k. Note
that the V
IN
falling threshold will be 10% less than the
rising threshold or 11V.
Since the maximum V
IN
is more than 4.5x the UVLO thresh-
old, a 4.7
V Zener diode in parallel with R4 is required to
keep the maximum voltage on the RUN pin less than the
absolute maximum of 6V.
The I
SET
pin should be left open in this example to select
maximum peak current (1.2A typical). Figure 11 shows a
complete schematic for this design example.
V
FB
SW
10µH
V
IN
RUN
200k
2.2µF
47µF
V
OUT
3.3V
500mA
V
IN
24V
21k
4.7V
3630a F11
SS
V
PRG2
V
PRG1
FBO
I
SET
GND
LTC3630A
Figure 11. 24V to 3.3V, 500mA Regulator at 200kHz

LTC3630AEMSE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Efficiency, 76V 500mA Synchronous Step-Down Converter
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union