LTC3630A
9
3630afc
For more information www.linear.com/LTC3630A
operaTion
The LTC3630A is a synchronous step-down DC/DC con-
verter with internal power switches that uses Burst Mode
control.
The low quiescent current and high switching
frequency results in high efficiency across a wide range
of load currents. Burst Mode operation functions by using
short “burst” cycles to switch the inductor current through
the internal power MOSFETs, followed by a sleep cycle
where the power switches are off and the load current is
supplied by the output capacitor. During the sleep cycle,
the LTC3630A draws only 12µA of supply current. At light
loads, the burst cycles are a small percentage of the total
cycle time which minimizes the average supply current,
greatly improving efficiency. Figure 1 shows an example
of Burst Mode operation. The switching frequency and the
number of switching cycles during Burst Mode operation
are dependent on the inductor value, peak current, load
current, input voltage and output voltage.
reducing the V
IN
pin supply current to only 12µA. As the
load current discharges the output capacitor, the voltage
on the V
FB
pin decreases. When this voltage falls 5mV
below the 800mV reference, the feedback comparator
trips and enables burst cycles.
At the beginning of the burst cycle, the internal high side
power switch (P-channel MOSFET) is turned on and the
inductor current begins to ramp up. The inductor current
increases until either the current exceeds the peak cur
-
rent comparator
threshold or the voltage on the V
FB
pin
exceeds 800mV, at which time the high side power switch
is turned off and the low side power switch (N-channel
MOSFET) turns on. The inductor current ramps down until
the reverse current comparator trips, signaling that the
current is close to zero. If the voltage on the V
FB
pin is
still less than the 800mV reference, the high side power
switch is turned on again and another cycle commences.
The average current during a burst cycle will normally be
greater than the average load current. For this architecture,
the maximum average output current is equal to half of
the peak current.
The hysteretic nature of this control architecture results
in a switching frequency that is a function of the input
voltage, output voltage, and inductor value. This behavior
provides inherent short-circuit protection. If the output is
shorted to ground, the inductor current will decay very
slowly during a single switching cycle. Since
the high side
switch turns on only when the inductor current is near zero,
the LTC3630A inherently switches at a lower frequency
during start-up or short-circuit conditions.
Start-Up and Shutdown
If the voltage on the RUN pin is less than 0.7V, the
LTC3630A enters a shutdown mode in which all internal
circuitry is disabled, reducing the DC supply current to
5µA. When the voltage on the RUN pin exceeds 1.21V,
normal operation of the main control loop is enabled. The
RUN pin comparator has 110mV of internal hysteresis,
and therefore must fall below 1.1V to stop switching and
disable the main control loop.
An internal 0.8ms soft-start function limits the ramp rate
of the output voltage on start-up to prevent excessive input
supply droop. If a longer ramp time and consequently less
BURST
FREQUENCY
CURRENT
OUTPUT
VOLTAGE
∆V
BURST
CYCLE
CYCLE
SWITCHING
FREQUENCY
Figure 1. Burst Mode Operation
Main Control Loop
The LTC3630A uses the V
PRG1
and V
PRG2
control pins to
connect internal feedback resistors to the V
FB
pin. This
enables fixed outputs of 1.8V, 3.3V or 5V without increas-
ing component
count, input supply current or exposure to
noise on the sensitive input to the feedback comparator.
External feedback resistors (adjustable mode) can still
be used by connecting both V
PRG1
and V
PRG2
to ground.
In adjustable mode the feedback comparator monitors
the voltage on the V
FB
pin and compares it to an inter-
nal 800mV reference.
If this voltage is greater than the
reference, the comparator
activates a sleep mode in which
the power switches and current comparators are disabled,
(Refer to Block Diagram)
