ICS85322I Data Sheet DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V/3.3V LVPECL TRANSLATOR
ICS85322I REVISION D MARCH 6, 2014 15 ©2014 Integrated Device Technology, Inc.
Revision History Sheet
Rev Table Page Description of Change Date
A 8 Added Termination for LVPECL Outputs section. 5/30/02
A
6
7
3.3V Output Load Test Circuit Diagram, corrected V
EE
= -1.3V ± 0.135V
to read V
EE
= -1.3V ± 0.165V.
Updated Output Rise/Fall Time Diagram.
8/23/02
B
T2 2
3
6
7
Pin Characteristics Table - changed C
IN
4pF max. to 4pF typical.
Absolute Maximum Ratings, updated Inputs ratings.
Updated 3.3V LVPECL Output Termination Diagrams.
Added Termination for 2.5V LVPECL Outputs.
Updated format throughout data sheet.
10/7/03
C
T2
T3C
T3F
T8
1
2
3
4
8-9
12
Features Section - added lead-free bullet.
Pin Characteristics Table - deleted RPulldown row.
LVPECL 3.3V DC Characteristics Table -corrected V
OH
max. from V
CC
- 1.0V to
V
CC
- 0.9V; and V
SWING
max. from 0.85V to 1.0V.
LVPECL 2.5V DC Characteristics Table -corrected V
OH
max. from V
CC
- 1.0V to
V
CC
- 0.9V; and V
SWING
max. from 0.85V to 1.0V.
Power Considerations - corrected power dissipation to reflect V
OH
max in Table 3C & 3F.
Ordering Information Table - added lead-free part number, marking, and note.
4/11/07
D
T8
12
14
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefix from Part/Order Number column.
Added Contact Page.
7/28/10
D
T5
T6
1
3
8
10
12
Added TSSOP package information.
Changed ‘Package Thermal Impedance,
JA
– 112.7°C/W (0 lfpm)’ to
‘Junction Temperature, T
J
– 125°C”.
Updated Power Considerations.
Replaced Thermal Resistance
JA
table with 8-Lead TSSOP/SOIC.
Replaced
JA
vs. Air Flow table with 8-Lead TSSOP/SOIC.
Added Package drawing for 8-Lead TSSOP.
3/10/14
