ICS85322I Data Sheet DUAL LVCMOS/LVTTL-TO-DIFFERENTIAL 2.5V/3.3V LVPECL TRANSLATOR
ICS85322I REVISION D MARCH 6, 2014 9 ©2014 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the IDT85322I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT85322I is the sum of the core power plus the power dissipated at the output(s).
The following is the power dissipation for V
CC
= 3.3V +5% 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated at the outputs.
• Power (core)
MAX
=V
CC_MAX
*I
EE_MAX
= 3.465V * 25mA = 86.6mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_
MAX
(3.465V, with all outputs switching) = 86.6mW + 60mW = 146.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient ther mal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 157°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.147W * 157°C/W = 108.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 5. Thermal Resistance
JA
for 8-Lead TSSOP/SOIC
NOTE: Above
JA
values are the simulation result using JEDEC Standard Multi-Layer Test Board.
JA
by Velocity
Meters per Second 012
8-Lead TSSOP 157°C/W 154°C/W 151°C/W
8-Lead SOIC 103°C/W 94°C/W 89°C/W
