Data Sheet SSM2517
Rev. B | Page 3 of 16
SPECIFICATIONS
PVDD = 5.0 V, VDD = 1.8 V, f
S
= 128×, T
A
= 25°C, R
L
= 8 Ω + 33 μH, unless otherwise noted. When f
S
= 128×, PDM clock = 6.144 MHz;
when f
S
= 64×, PDM clock = 3.072 MHz.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power P
O
f = 1 kHz, BW = 20 kHz
R
L
= 4 Ω, THD = 1%, PVDD = 5.0 V 2.4 W
R
L
= 8 Ω, THD = 1%, PVDD = 5.0 V 1.38 W
R
L
= 4 Ω, THD = 1%, PVDD = 3.6 V 1.2 W
R
L
= 8 Ω, THD = 1%, PVDD = 3.6 V 0.7 W
R
L
= 4 Ω, THD = 10%, PVDD = 3.6 V 1.5 W
R
L
= 8 Ω, THD = 10%, PVDD = 3.6 V 0.9 W
Total Harmonic Distortion Plus Noise THD + N f = 1 kHz, BW = 20 kHz
P
O
= 100 mW into 8 Ω, PVDD = 3.6 V 0.035 %
P
O
= 500 mW into 8 Ω, PVDD = 3.6 V 0.1 %
P
O
= 1 W into 8 Ω, PVDD = 5.0 V 0.12 %
R
L
= 4 Ω, −6 dBFS input, PVDD = 5.0 V 3.6 %
R
L
= 8 Ω, −6 dBFS input, PVDD = 5.0 V 1.0 %
R
L
= 4 Ω, −6 dBFS input, PVDD = 3.6 V 5.2 %
R
L
= 8 Ω, −6 dBFS input, PVDD = 3.6 V 2.3 %
Efficiency η P
O
= 2.4 W into 4 Ω, PVDD = 5.0 V 86 %
P
O
= 1.38 W into 8 Ω, PVDD = 5.0 V 92 %
Average Switching Frequency f
SW
No input 290 kHz
Closed-Loop Gain Gain
−6 dBFS PDM input, BTL output,
f = 1 kHz
PVDD = 3.6 V 3.5 V
P
PVDD = 5.0 V 4.78 V
P
Differential Output Offset Voltage V
OOS
Gain = 6 dB 0.5 mV
Low Power Mode Wake Time t
WAKE
0.5 ms
Input Sampling Frequency f
S
f
S
= 64× 1.84 3.072 3.23 MHz
f
S
= 128× 3.68 6.144 6.46 MHz
POWER SUPPLY
Supply Voltage Range
Amplifier Power Supply PVDD 2.5 3.6 5.5 V
Digital Power Supply VDD 1.62 1.8 3.6 V
Power Supply Rejection Ratio PSRR
GSM
V
RIPPLE
= 100 mV at 217 Hz 85 dB
Supply Current, H-Bridge I
PVDD
Dither input, 8 Ω + 33 μH load
PVDD = 5.0 V, f
S
= 64× 3.1 mA
PVDD = 5.0 V, f
S
= 128× 3.2 mA
PVDD = 3.6 V, f
S
= 64× 2.6 mA
PVDD = 3.6 V, f
S
= 128× 2.7 mA
PVDD = 2.5 V, f
S
= 64× 2.2 mA
PVDD = 2.5 V, f
S
= 128× 2.3 mA
Standby Current PVDD = 5.0 V 0.0 mA
Power-Down Current 100 nA
Supply Current, Modulator I
VDD
Dither input, 8 Ω + 33 μH load
VDD = 3.3 V, f
S
= 64× 1.3 mA
VDD = 3.3 V, f
S
= 128× 2.4 mA
VDD = 1.8 V, f
S
= 64× 0.6 mA
VDD = 1.8 V, f
S
= 128× 1.2 mA
SSM2517 Data Sheet
Rev. B | Page 4 of 16
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Standby Current VDD = 1.8 V, f
S
= 64× 57 μA
VDD = 1.8 V, f
S
= 128× 114 μA
Shutdown Current VDD = 3.3 V 3.0 μA
VDD = 1.8 V 0.9 μA
NOISE PERFORMANCE
Output Voltage Noise e
n
Dithered input, A-weighted
PVDD = 3.6 V, f
S
= 64× 43 μV
PVDD = 3.6 V, f
S
= 128× 52 μV
PVDD = 5.0 V, f
S
= 64× 52 μV
PVDD = 5.0 V, f
S
= 128× 60 μV
Signal-to-Noise Ratio SNR
P
O
= 1.38 W, PVDD = 5.0 V, R
L
= 8 Ω,
A-weighted
f
S
= 64× 96 dB
f
S
= 128× 95 dB
DIGITAL INPUT SPECIFICATIONS
Table 2.
Parameter Symbol Min Typ Max Unit
INPUT SPECIFICATIONS
Input Voltage High V
IH
PCLK, PDAT, LRSEL Pins 0.7 × VDD 3.6 V
GAIN_FS Pin 1.35 5.5 V
Input Voltage Low V
IL
V
PCLK, PDAT, LRSEL Pins −0.3 0.3 × VDD V
GAIN_FS Pin −0.3 +0.35 V
Input Leakage High I
IH
PDAT, LRSEL, GAIN_FS Pins 1 μA
PCLK Pin 3 μA
Input Leakage Low I
IL
PDAT, LRSEL, GAIN_FS Pins 1 μA
PCLK Pin 3 μA
Input Capacitance 5 pF
Data Sheet SSM2517
Rev. B | Page 5 of 16
PDM INTERFACE DIGITAL TIMING SPECIFICATIONS
Table 3.
Limit
Parameter
t
MIN
t
MAX
Unit Description
t
DS
44 ns Valid data start time
1
t
DE
7 ns Valid data end time
1
1
The SSM2517 was designed so that the data line can transition coincident with or close to a clock edge. It is not necessary to delay the data line transition until after the
clock edge because the SSM2517 does this internally to ensure good timing margins. The data line should remain constant during the valid sample period illustrated
in Figure 2; it may transition at any other time. Timing is measured from 70% of VDD on the rising edge or 30% VDD on the falling edge.
Timing Diagram
09211-002
t
DS
t
DE
PCLK
PDAT
VALID LEFT SAMPLE VALID LEFT SAMPLEVALID RIGHT SAMPLE
Figure 2. PDM Interface Timing

SSM2517CBZ-R7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Audio Amplifiers Digital PDM-Input Mono 2.5W Class-D
Lifecycle:
New from this manufacturer.
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